can anybody help me in to remove this error......! full_adder.vhd(18): near "is": expecting: END in following code of full adder......!

[MNaee]

library IEEE;

use IEEE.STD_LOGIC_1164.ALL;

entity full_adder is

port ( -- Eingaben

a    : in std_logic ;

b    : in std_logic ;

c    : in std_logic ;

sum_full   : out std_logic ;

carry_full  : out std_logic 

);

end full_adder;

architecture behavior of full_adder is

signal sum1, sum2 ,carry1, carry2 : bit ;

component half_adder is--asc

port ( -- Eingaben

   a    : in std_logic ;

   b    : in std_logic ;

   sum   : out std_logic ;

   carry  : out std_logic 

   );

 end component half_adder;

begin

p1 : process

begin 

HA1 : port map half_adder (

        a => a,

        b => b,

        sum => sum1 ,

        carry => carry1

         );

HA2 : port map 

      half_adder(

        a => sum1,

        b => c,

        sum => sum2 ,

        carry => carry2

         );

end process;         

  sum_full <= sum2 ;

  carry_full <= carry1 or carry2 ;        

end behavior;

[Tricky]

You are trying to instantiate components inside a process. You can't do that

[Abe · Accepted solution]

First off, there are quite a few issues with your code. I'll highlight them here:

1. You've declared sum and carry outputs as std_logic, while the intermediate signals carry1, etc as bit. This is a type mismatch. You need to declare these also as std_logic.
2. You've used a process for generating combinational logic. The general rule of design is that we use continuous assignments for combinational logic and Process for sequential logic.
3. When using a Process, you must specify a Sensitivity list, ex, Process (a,b,c). If you do not specify this , the compiler may treat this as an infinite process loop and can generate errors.
4. The Port mapping is wrong, it should be as

label/instance_name : component_name Port Map

(

... );

Make these changes to your code and it will compile without errors.

[MNaee]

Thanks for the reply........!

problem is resolve by correct instantiation, removing process and and declaring signal as std_logic, also i removed 'is' and 'half_adder' near end of component declaration.