I am having a frustrating issue where i am unable to generate a ddr3 core throught the ip catalog.I configure the core i want in the ip catalog and when go to generate the generation wizard hangs Info: ddr3_gen_0: Variation language : VHDL Info: ddr3_gen_0: Output directory : C:\repos\ddr3_ref_design Info: ddr3_gen_0: Generating variation file C:\repos\ddr3_ref_design\ddr3_gen_0.vhd Info: ddr3_gen_0: Generating synthesis files Info: Generating altera_mem_if_ddr3_emif "ddr3_gen_0" for QUARTUS_SYNTH Info: "ddr3_gen_0" instantiated altera_mem_if_ddr3_emif "ddr3_gen_0" Info: "ddr3_gen_0" instantiated altera_mem_if_ddr3_pll "pll0" Info: Generating clock pair generator Info: Generating altgpio Info: Info: ***************************** Info: Info: Remember to run the ddr3_gen_0_p0_pin_assignments.tcl Info: script after running Synthesis and before Fitting. Info: Info: ***************************** Info: Info: "ddr3_gen_0" instantiated altera_mem_if_ddr3_phy_core "p0" Info: "ddr3_gen_0" instantiated altera_mem_if_ddr3_afi_mux "m0" The wizard never get past this point..... I have tried this on quartus 15.0/16.0/17.1 on both lite and full versions of the software and it always hangs at this point... I dont know what to do? Any suggestions? Thanks
What's your target device and how long have you waited for it before thinking that it's hung? Were there any warnings in the IP Parameter Editor (or is it the Megawizard) that appear before you try to generate?
I am targetting the Max10 speed grade 6. The only warnings i get are:Warning: ddr3_max_111: ODT is disabled. Enabling ODT (Mode Register 1) may improve signal integrity Warning: ddr3_max_111.pll_bridge: pll_bridge.pll_sharing cannot be both connected and exported I am assuming the ODT is not the problem since it has to do with signal integrity. The second warning can be ignored according to: https://www.altera.com/support/support-resources/knowledge-base/solutions/fb203048.html I have let the wizard run over night and it still doesn't make it any further then described above...
Can you post the parameter settings you've chosen? Perhaps you've put in a mix that is not supported on your device but for some reason isn't causing the generation to fail.
Have you solved this issue?The same issue occurs when I use ddr3 controller IP 17.1 & 18.0. While I used my classmate's pc to do this , it can be finished rapidly. Both of our os are win10 1709. And we have used the same install pack.