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Does anyone knows of a way to tell Quartus that a particular FF is a clock-domain-crossing FF so that post-route netlist instantiates a FF for that, which does not propagate "X".
regards, KostasLink Copied
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Can you explain more what you're trying to do? There is only one type of FF in the fabric, so it can't choose anything different to instantiate. Are you talking about for simulation or something?
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I am talking about timing simulation. I want to do SDF-simulation of a routed design that has a async FF (asymc means that data-in may violate setup/hold requirements). I've taken care of metastability by using a two-stage FF synchronization, the problem is that during timing simulation if setup/hold is violated then the output of the first-stage FF will go to "X". Of course at the next clock cycle it will get a valid value; but in the meantime the "X" will propagate into the other clock domain.
I used to have this problem at a Xilinx project as well; the solution was to apply an ASYNC_REG attribute on these FFs. This attribute instructs the Xilinx tools to instantiate a special FF in the generated post-route simulation netlist. Actually the instantiated FF was a standard FF but with the generic XON set to false. This generic causes the FF to drive its output to its previous value if a violation occurs. I checked the respective Altera library component (called stratixii_lcell_ff) which has also such a generic that presumably does the same thing. I can solve the problem by manually altering the generated VHDL file but would like to avoid that. The solution would be to find a way to instruct Quartus to use FF with XON set to false for these particular registers. Sorry for the lengthy explanation.- Mark as New
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On a bulletin board, a lengthy explanation is ten times better than a brief explanation.
I believe in the Assignment Editor you can add: Show 'X' on timing violation = Off I've never used it before, but I think it's what you want.- Mark as New
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This seems to be the solution.. thank you very much Rysc..
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