generate clock with Quartus 7.1 web adition

[Altera_Forum]

Hello everyone, 

 I've asked here before how can I make the FPGA generate a clock with Quartus 7.1.  I read the user guide you told me and I used the MegaWizard Plug-In Manager (ALTPLL) in order to do it.  after the wizard is dune, the Quartus is creating a new verilog file with the module that multiplies the input clock frequency. I want to combine this file with another module I made, and I can't understand how to do it.   Sorry if my question is stupid. As I mentioned before, I'm new to verilog and Quertus.

[Altera_Forum]

If you are using HDL flow, you should use the instance that is generated by megawizard. Refer to the generated verilog or vhdl file for this. Wire the input/output in your design file for the generated pll just like you connect any other modules in HDL design flow and you can use this pll in your design. 

 If you are using schematic flow, you should use the generated bsf file of the pll. You may have to generate the bsf for your design file. If you are using SOPC builder flow, the bsf for your system must have been automatically generated by SOPC builder.

[Altera_Forum]

You can use "map" in vhdl. A handbook is good for you. 

You can also do as follows.After compiling your project(written with vhdl or verilog),"File\Create/update\Create sambol files for current file", then you can insert it in your other projects. Hope it can help you! Regards.

[Altera_Forum]

I am going to work from a more basic level. 

In general, you Cannot make the FPGA generate a clock.  You must provide a clock into the FPGa from something like an Oscillator, or from some other chip that can generate a clock source like a Dallas Semiconductor (now Maxim) clock source device.  YOu can then feed that clock into the FPGA for clocking elements in the FPGA. From there, you can feed the clock into a PLL to generate many different clock outputs for use both internal to and external to the FPGA.  I hope this adds a little more clarity to your question. Avatar

[Altera_Forum]

You know that we often need to draw PCB. We have the chip which program was downloaded , in order to make the chip work ,we need to add C and R to the PCB,of course the clock. 

Avatar is all right. The clock you can define is just what Quartus do ,but it is not really real in your PCB. Regards.

[Altera_Forum]

In the same kind of subject, I generated a PLL with the ALTPLL function, but even when the compilation is okay after inserting an instance in my design, it's impossible to simulate nor synthetise it in Quartus... Is therer a basic standard process in order to do that properly ? The Cyclone II Handbook isn't very complete in how to do that. 

Thank you very much!

[Altera_Forum]

As complement I have the following error message when compiling in ModelSim: 

# ** Warning: [1] C:/hard/src/ezPciE_pll.vhd(202): No default binding for component 'altpll'. (No entity named 'altpll' was found.) That's quite odd, because all the entities are present, so are the librairies (including altera_mf)..

[Altera_Forum]

Hi Pookipsit, in case you haven't got your answer yet, when you run your megawizard, you can specify the output file name. That is the module name that will be created (e.g. mypll). You can instantiate the "mypll" - output file name that you name in another verilog code. For example: 

  mypll PLL0(  .inclk0(clk),  .c0(pll_out));  Download the design example at http://www.altera.com/support/examples/modelsim/exm-siigx-timing-vhdl-msaltera.html  You can see how the top-level alt2gxb_example.v instantiate the mypll in mypll.v (generated by Megawizard). Hope it helps.

[Altera_Forum]

Hi Marc, this is weird. Do you specify the library altera_mf using the "-L" switch when you simulate your source code? For example to run RTL simulation: 

 vsim -t 1ps -L lpm_ver -L altera_ver -L altera_mf_ver -L sgate_ver -L rtl_work -L work an_dcfifo_top_vlg_vec_tst  If not sure, you can try run the native-link (Tools->EDA Simulation Tool->RUN EDA RTL Simulation) see whether you get the same error. Hope it helps.

[Altera_Forum]

Thank you very much guruDog, it was a mapping problem into ModelSim. 

 Thanks for your answer :)

[Altera_Forum]

--- Quote Start ---  In general, you Cannot make the FPGA generate a clock. You must provide a clock into the FPGa from something like an Oscillator, or from some other chip that can generate a clock source like a Dallas Semiconductor (now Maxim) clock source device.  --- Quote End ---    Avatar,  This is exactly what I was going to point out to myself in a response to a question I was about to post. However, I must still ask:  Why is there# xx delay statement in Verilog or to put it another way - why are there so many examples of how we can "generate" a clock with:   @always# 10 q= ~q  That never made sense to me? How would the FPGA know what the length of 10 time units is and where do the time units come from in the first place? Is this some evil compiler thing or does it exist PURELY SYNTHENICALLY only within the software environment for the purpose of testing and simulation?  And even if this is synthetic concept, how does one tell the compiler what one time unit is and where is the counting kept for this to work? Is it all transparent to the Quartus2 user?   In my mind I see serious conceptual problems when I encounter “assign# xx” statements. I would appreciate another blunt to-the-money paragraph on this if you have the time.  Thanks much ~B