Intel® Quartus® Prime Software
Intel® Quartus® Prime Design Software, Design Entry, Synthesis, Simulation, Verification, Timing Analysis, System Design (Platform Designer, formerly Qsys)
17255 Discussions

clock type mismatch in incremental compiles

Altera_Forum
Honored Contributor II
‎03-05-2012 08:01 PM
1,714 Views

I have a design that is partitioned, logic-logic locked and subsequently placed and routed successfully. But later when I recompile the design with some changes in a different area of the design, I get clock type mismatch errors such as - 

 

Error (176363): Can't use clock type Regional Clock at location CLKCTRL_R32 for clock control block or source node control_link:pf_link|control_link_slite2_top:control_link_slite2_top_inst|control_link_slite2_xcvr:xcvr_inst|alt4gxb:alt4gxb_component|alt4gxb_03t9:auto_generated|tx_clkout[0] with clock type Periphery Clock -- clock types do not match 

 

 

The design partition properties are set to use post-fit netlist including routing information. The logic-lock properties are set to fixed. Making the region reserved in logic-lock properties doesn't help. 

 

Any ideas? I cannot figure out what is causing Quartus (11.1 sp2) to loose the routing information. 

 

TIA 

Sanjay
0 Kudos

Link Copied

2 Replies
Altera_Forum
Honored Contributor II
‎03-05-2012 08:20 PM
988 Views

If I were to take a guess, it is locked to CLKCTRL_R32 but the internal promotion is making it a periphery clock. I don't believe assigning a clock to a specific location such as CLKCTRL_R32 guarantess it will be promoted to a regional. (It seems silly, but very seldom do users lock down to specific Regional locaitions). Now, when I've used partitions set to post-fit, this has always been resolved for me through the partition, so not sure why it wouldn't occur here, unless perhaps the source transceiver is outside of the partition? Just a guess. Maybe take that name into the Assignment Editor and make a Global assignment of type Regional. Just a guess though.

0 Kudos
Copy link
Altera_Forum
Honored Contributor II
‎03-12-2012 10:44 PM
988 Views

These didn't help.  

 

But I am puzzled as to why none of the clocking and calibration features such as PLLs, DLLs, calibration blocks, etc. are not included in the design partition statistics. 

 

Altera support asked me to add this to quartus.ini - fsac_clock_manager_merge_all_hssi_tx_pcs_in_same_quad=off 

 

Not sure what it does but I have since then started getting internal error when I recompile with an existing database. 

 

----------error msg begin ---------- 

Internal Error: Sub-system: CDB_ATOM, File: /quartus/db/cdb_atom/cdb_atom_tgx_lcell.cpp, Line: 854 

Atom# 406195 - get_lutmask() called for non-consistent arithmetic lcell comb 

Stack Trace: 

0x13d66d: CDB_ATOM_TGX_LCELL_COMB::get_transformed_lutmask + 0x57d (db_cdb_atom) 

0x13dd60: CDB_ATOM_TGX_LCELL_COMB::get_lutmask + 0x160 (db_cdb_atom) 

0x18744e: CDB_ATOM_LUTMASK_CACHE::visit_atom_tgx_lcell_comb + 0xae (db_cdb_atom) 

0x186aff: CDB_ATOM_LUTMASK_CACHE::init_data + 0x7f (db_cdb_atom) 

0x186dd2: CDB_ATOM_LUTMASK_CACHE::CDB_ATOM_LUTMASK_CACHE + 0x92 (db_cdb_atom) 

0x188967: CDB_ATOM_LUTMASK_CACHE::init_lutmask_cache + 0xe7 (db_cdb_atom) 

0xb62a: a2t_call_update_tdb_netlist_for_atoms + 0x9f7a (tsm_a2t) 

0xbf74: a2t_call_update_tdb_netlist_for_atoms + 0xa8c4 (tsm_a2t) 

0xd54a: a2t_call_recursive_visitor + 0xa (tsm_a2t) 

0x3fa7: sta_update_tdb_netlist_for_atoms + 0xe67 (TSM_STA) 

0xb98b: sta_build_and_preprocess_tdb + 0x15b (TSM_STA) 

0x164a4: tdc_get_accessories + 0x53c4 (TSM_TDC) 

0xef93a: FITCC_TDC_UTILITY::setup_tdc_utility + 0x4ba (FITTER_FITCC) 

0xf1fa9: FITCC_TDC_UTILITY::FITCC_TDC_UTILITY + 0x1e9 (FITTER_FITCC) 

0x3a42b: FITCC_ENV::get_tdc_utility_or_create_if_necessary + 0x35b (FITTER_FITCC) 

0x217e3e: FSAC_AUTO_DELAY_CHAIN_OP::work_new + 0x1be (FITTER_FSAC) 

0x1fda49: FSAC_DELAY_CHAIN_OP::work + 0x1d9 (FITTER_FSAC) 

0x84ce: FTITAN_LUT_RAM_CONVERSION_UTIL::lutram_iterm_port_is_internal_registered + 0x4c1e (fitter_ftitan) 

0x462f7: FITCC_EXPERT::fitter_post_operations + 0x1a7 (FITTER_FITCC) 

0x475c5: FITCC_EXPERT::invoke_fitter + 0xa55 (FITTER_FITCC) 

0x29c5: ftitan_execute + 0x265 (fitter_ftitan) 

0xb55d: fmain_start + 0x7cd (FITTER_FMAIN) 

 

 

0x1264b: qexe_get_command_line + 0x1c5b (comp_qexe) 

0x1588d: qexe_process_cmdline_arguments + 0x5ad (comp_qexe) 

0x159a1: qexe_standard_main + 0xa1 (comp_qexe) 

 

0x1a48: MSG_INITIALIZER::~MSG_INITIALIZER + 0x118 (CCL_MSG) 

0x19ec: MSG_INITIALIZER::~MSG_INITIALIZER + 0xbc (CCL_MSG) 

0x53d4: MEM_INITIALIZER::~MEM_INITIALIZER + 0x244 (ccl_mem) 

0x3379f: msg_exe_main + 0x8f (CCL_MSG) 

 

0x1652c: BaseThreadInitThunk + 0xc (kernel32) 

0x2c520: RtlUserThreadStart + 0x20 (ntdll) 

 

End-trace 

 

Quartus II 64-Bit Version 11.1 Build 259 01/25/2012 SJ Full Version 

Service Pack Installed: 2 

 

----------- error msg end -------------
0 Kudos
Copy link
Reply

Community support is provided Monday to Friday. Other contact methods are available here.

Intel does not verify all solutions, including but not limited to any file transfers that may appear in this community. Accordingly, Intel disclaims all express and implied warranties, including without limitation, the implied warranties of merchantability, fitness for a particular purpose, and non-infringement, as well as any warranty arising from course of performance, course of dealing, or usage in trade.

For more complete information about compiler optimizations, see our Optimization Notice.