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I am trying to implement the table for cordic algorithm. However, I got several critical warning messages:
1. No exact pin location assignment for the pins. 2. Synopsys Design Constaints File not found: 'lut.sdc', which is required by TimeQuest Timing Analyzer to get proper timing constrainsts. The file is attached. Does anybody have any idea on how to fix the above two warnings? Thanks in advance.Link Copied
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--- Quote Start --- 1. No exact pin location assignment for the pins. --- Quote End --- Open the pin assignment tool from Quartus menu bar and assign your design I/O signals to proper FPGA pins --- Quote Start --- 2. Synopsys Design Constaints File not found: 'lut.sdc', which is required by TimeQuest Timing Analyzer to get proper timing constrainsts. --- Quote End --- Create a lut.sdc file and add at least the minimal constraints. Read the TQ tutorial if you don't know how to.
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I tried some other simple design examples, and I have never had the need to create this file (lut.sdc) myself. What made everything different here?
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--- Quote Start --- I tried some other simple design examples, and I have never had the need to create this file (lut.sdc) myself. What made everything different here? --- Quote End --- I guess so far you copied and modified design examples which already contained all the required files. If you started your current design from scratch you need to define constraint files besides HDL code.
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"create a lut.sdc file and add at least the minimal constraints. read the tq tutorial if you don't know how to." Do you have a recommendation on a good tutorial with examples I could use in order to make this .sdc file?
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A good start is the TQ user guide by forum user Rysc: http://www.alterawiki.com/wiki/timequest_user_guide
IMHO this is better than the 'official' Altera TQ tutorial. In the beginning you probably don't need to read it all. If you want to build a basic sdc file, simply follow the guidelines in the first part of section 3 (pages 72 to 77)
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