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Any good tutorial with examples to setup the .sdc file? Besides, is it possible to generate the Verilog files based on a schematic file (.bdf)?
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U can search at www.altera.com, there are some document on the timing analysis, which should have note on the sdc.
Foe generate the verilog, after u compile the design using Quartus II, u can generate verilong netlist using netlist writer.- Mark as New
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--- Quote Start --- Any good tutorial with examples to setup the .sdc file? --- Quote End --- timequest user guide (http://www.alterawiki.com/wiki/timequest_user_guide) --- Quote Start --- Besides, is it possible to generate the Verilog files based on a schematic file (.bdf)? --- Quote End --- Yes. In Quartus II: File -> Create / Update -> Create HDL Design File from Current File... Or you can use netlist as tancheeseng84[/b] (http://www.alteraforum.com/forum/member.php?u=73976)[/b] suggested.

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