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Hi..I am new to quartus and I am currently working on an 32 bit addition/subtractor block. First I thought that my .bdf files are erroneous because whenever I input a .vwf file(containing the input output nodes of my circuit) and simulate it with quartus simulator--->timing simulation; the simulator displays only a window that exits instantly . The bigger problem is that it doesn't display any output waveform. Out of curiosity I design a simpler circuit....an ordinary AND gate.:) and created the corresponding inputs in the simulation waveform editor, but the same problem arised....... Lastly I noticed that simulator produces a ****.vwf.temp file.
I am currently using Quartus II Web Edition version 13.0 in my 32 bit Windows 7 starter computer... I also followed the manual from I hope somebody can help me with this problem. Thanks alot for any response....Link Copied
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Hi,
not sure of this applies to you (found it on the web) but have you compiled your design completely (including Fitter)? I'm astonished to see some kind of simulator's revival in QII 13, a little bit hidden as it's not (as earlier) in Tools but with File, new, University Program VWF. Seems like ALTERA rates this tool (as on their HP) as a support for students rather a tool engineers would use...
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