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constraints

ymiler
Employee
544 Views

Hi

I have an issue about constraints in Quartus  :

 

Its regarding the follow constraint :

 

set_instance_assignment -name FAST_OUTPUT_ENABLE_REGISTER ON -to * -entity <entity name>

 

I  have 2 question :

 

1)What is the different between

 

  1. a) set_instance_assignment -name FAST_OUTPUT_ENABLE_REGISTER ON -to *    -entity <entity name>
  2. b) set_instance_assignment -name FAST_OUTPUT_ENABLE_REGISTER ON -to *

 

Does implementation behave differently when  -entity <entity name> not exist in the end line of the constraint ?

 

2)My project includes  simple mux that generate IO  high-Z

   assign output_sig = sel ? 1’b0 : 1’bz ;  ( ‘sel’  is a register )

 

  I succeed to create high-Z on signal “output_sig” only  in the following situation : (verify in the lab)

set_instance_assignment -name FAST_OUTPUT_ENABLE_REGISTER ON -to *    -entity <entity name>     

  or     FAST_OUTPUT_ENABLE_REGISTER ON constraint doesn’t define at all

 

but ,  when the constraint is

          set_instance_assignment -name FAST_OUTPUT_ENABLE_REGISTER ON -to *    

 without -entity <entity name> the implementation doesn’t succeed to create high -Z (verify in the lab)

 

please advise ,

0 Kudos
12 Replies
SyafieqS
Moderator
520 Views

Miller,


In that case, you should use with the -entity option. This will implements an output enable register in an I/O cell with a fast, direct connection to an I/O pin more accurate according to the hierarchy.


SyafieqS
Moderator
499 Views

May I know if there is any update?


ymiler
Employee
495 Views

My code includes the follow lines :

 

reg [9:0] cnt ='b0;
reg       en  ='b0;
always @(posedge clk10 )
  begin
      cnt = cnt + 1'b1 ;
      if (cnt == 10'b1111111111 )
          en = !en ; 
  end
assign A = en ? 1'bz : 1'b0 ; 

In addition , my qsf file include the line :

set_instance_assignment -name FAST_OUTPUT_ENABLE_REGISTER ON -to *

 

this code should implement other drive each 1ms 

1ms - high Z

1ms- '1b0

when I test I in the lab - the scope show steady 1'b0 ( I use pull up transistor to recognize 1'b0 / 1'bz )

 

Then - I found  out warnings in the fit.plan.rpt 

 

Warning (176225): Can't pack node en_Z~_Duplicate_1 to I/O pin File: /tmp/ymiller/Premier/snj_mrp_bt_1_2_RTL49_1_RST_fpga_22ww06_01_083417/rev_MX/par_1/premier_fpga_top.vqm Line: 840
Warning (176260): Can't pack node en_Z~_Duplicate_1 and I/O node en_RNO -- one node must be a logic cell and one must be an I/O cell File: /tmp/ymiller/Premier/snj_mrp_bt_1_2_RTL49_1_RST_fpga_22ww06_01_083417/rev_MX/par_1/premier_fpga_top.vqm Line: 840

 

Can you explain what is wrong in my simple code ? what should I change in the code in order to prevent from this warning 

Mybe when I fix it - my high Z implemetation will work 

 

Yishay

SyafieqS
Moderator
470 Views

Yishay,


I am checking this internally and will back with some findings


ShengN_Intel
Employee
452 Views

Hi Yishay,

 

There is nothing wrong with your code and settings in .qsf file. The .qsf file is just a setting file generated by Quartus so nothing will affect simulation if you make changes to .qsf file because that file is internally generated by Quartus. I try to simulate your code with modelsim and your code seems to work fine.

ShengN_Intel_0-1646805413988.png

Just you have to zoom out a bit because you got a big counter.

 

Thanks,

Best regards,
Sheng

SyafieqS
Moderator
436 Views

Yishay,


The simulation seem to work fine but not in hardware. Do you have any timing violation? May need to check and fix that first before running or hardware.


ymiler
Employee
392 Views

Hi

 

I just want to know why do I get the following message :

What will I changed in my code to prevent from the warnings

 

Warning (176225): Can't pack node en_Z~_Duplicate_1 to I/O pin File: /tmp/ymiller/Premier/snj_mrp_bt_1_2_RTL49_1_RST_fpga_22ww06_01_083417/rev_MX/par_1/premier_fpga_top.vqm Line: 840
Warning (176260): Can't pack node en_Z~_Duplicate_1 and I/O node en_RNO -- one node must be a logic cell and one must be an I/O cell File: /tmp/ymiller/Premier/snj_mrp_bt_1_2_RTL49_1_RST_fpga_22ww06_01_083417/rev_MX/par_1/premier_fpga_top.vqm Line: 840

 

What will I changed in my code to prevent from the warnings ?

SyafieqS
Moderator
327 Views

Yishay,


There is KDB related to your issue with reason as link below. May see if applicable or not.

https://www.intel.com/content/www/us/en/support/programmable/articles/000081521.html


ymiler
Employee
313 Views
SyafieqS
Moderator
265 Views

Yishay,


Let me know if there is any other concern on this.




ymiler
Employee
256 Views
SyafieqS
Moderator
176 Views

Since there is no update regarding this, thus I will put this case to close pending. Please post a response in the next 15 days to allow me to continue to support you. After 15 days, this thread will be transitioned to community support. The community users will be able to help you with your follow-up questions. 


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