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set false path in VHDL

AhmadZaklouta
Beginner
460 Views

I want to write sdc constraint for two signals in VHDL but I am not being able to understand the syntax.

the signals are term_count_internal and time_cnt_wrap_dly

 

this what I tried but it wrong:

attribute altera_attribute of rtl : architecture is
"-name SDC_STATEMENT""set_false_path -to [get_registers *time_cnt_wrap_dly*]";
   "-name SDC_STATEMENT""set_false_path -from [get_registers *term_count_internal*]""";
 
can someone guide me on this?
0 Kudos
12 Replies
sstrell
Honored Contributor III
451 Views
AhmadZaklouta
Beginner
440 Views

I read this but I want to have two set_false_path for two different signal and I am not being able to figure out the syntax.

SyafieqS
Moderator
438 Views

Ahmad,


You may want to take a look at the KDB below related embed sdc hdl. Hopes it will help as your reference.



SyafieqS
Moderator
438 Views
AhmadZaklouta
Beginner
433 Views

The VHDL syntax is not clear!
I have tried all these and non work:

 

attribute altera_attribute of rtl : architecture is "-name SDC_STATEMENT ""set_false_path -to [get_registers *time_cnt_wrap_dly*]"";""-name SDC_STATEMENT ""set_false_path -from [get_registers *term_count_internal*]""";

 

attribute altera_attribute of rtl : architecture is (
"-name SDC_STATEMENT ""set_false_path -to [get_registers *time_cnt_wrap_dly*]"";" &
"-name SDC_STATEMENT ""set_false_path -from [get_registers *term_count_internal*]""
);

 

attribute altera_attribute of rtl : architecture is 
"-name SDC_STATEMENT ""set_false_path -to [get_registers *time_cnt_wrap_dly*]"";" &
"-name SDC_STATEMENT ""set_false_path -from [get_registers *term_count_internal*]""";

 

sstrell
Honored Contributor III
425 Views

No offense, but is there a reason why you don't just use a separate .sdc file?  It will make your life much easier.

AhmadZaklouta
Beginner
418 Views

We are designing a library that is used accros multiple projects. so we don't have to write constraint for each project when it is embedded in the rtl.

SyafieqS
Moderator
391 Views

Ahmad,


May I know what Quartus version are you using? Std,Pro?

If Std, there might be some limitation in term of HDL construct and support thus prevent you from to do so.


AhmadZaklouta
Beginner
371 Views
SyafieqS
Moderator
322 Views

Ahmad,


Below are the syntax for altera_attribute package regarding the package for making assignments. Few restrictions of the implication which you can refer in below link for more details.


https://www.intel.com/content/www/us/en/programmable/quartushelp/17.0/hdl/vhdl/vhdl_file_dir_attribu...


Quartus only supports altera_attribute on entities, instances, ports, and registers. If applied to any other object, the synthesis attribute is ignored.


SyafieqS
Moderator
291 Views

Hi Ahmad,


May I know if there is any update?

Are you managed to work on the syntax?


SyafieqS
Moderator
258 Views

We do not receive any response from you to the previous reply that I have provided, thus I will put this case to close pending. Please post a response in the next 15 days to allow me to continue to support you. After 15 days, this thread will be transitioned to community support. The community users will be able to help you with your follow-up questions.


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