creating custom IP in platform designer

[UserID4331231]

How do you make Custome IP from verilog RTL file? whihc can be used in platform designer as a component ?
i tired using genric _component and added my RTL file as source file but upons saving as IP and generate HDL the "synth" folder was having an empty .v file.

can you share step by step guide on importing Verilog RTL file as custom IP and saving it?
I want to create such custom IP from RTL i write and share it with my team. Also once IP is created how can I update original RTL file for bug fixes and feature enhancements without
creating new IP everytime?

thanks

[sstrell]

For both Standard and Pro, you usually use the Component Editor in PD: https://www.intel.com/content/www/us/en/docs/programmable/683609/25-1/creating-components.html

You can create components starting with the generic component in Pro, but that's a more advanced flow, also documented in the user guide.

[KennyTan_Altera]

Not sure if you have update on the above? Do you still need more help? If no, we shall close this thread.

[KennyTan_Altera]

As we do not receive any response from you on the previous reply that we have provided. Please login to ‘https://supporttickets.intel.com/s/?language=en_US’, view details of the desire request, and post a feed/response within the next 15 days to allow me to continue to support you. After 15 days, this thread will be transitioned to community support. The community users will be able to help you on your follow-up questions.