dcfifo aclr recovery timming fail

[JDrba]

Timing analyzer tool report that Recovery timing on reset synchronizer fail. I found I can  apply the following false path assignment on the reset path:

set_false_path -to *dcfifo:dcfifo_component| dcfifo_*:auto_generated|dffpipe_*:wraclr|dffe*a[0] • set_false_path -to *dcfifo:dcfifo_component| dcfifo_*:auto_generated|dffpipe_*:rdaclr|dffe*a[0] 

Is it necessary use this to avoid timing violation or is it some another way?

[KhaiChein_Y_Intel]

Hi,

According to the user guide https://www.intel.com/content/dam/www/programmable/us/en/pdfs/literature/ug/ug_fifo.pdf (Page 19), you have to apply the above two false path assignments on the reset path.

Thanks.

Best regards,

KhaiY

[KhaiChein_Y_Intel]

Hi,

Do you have any questions?

Thanks.

Best regards,

KhaiY