已解决: ddr3 SRAM Controller with Uniphy intel FPGA IP 22.1 failed

jkhoo · ‎11-02-2023

Hi Intel team,

Please see below for the error message when i am generating the DDR3 IP.

<html>Info: "MyDDR3_master" instantiated altera_mem_if_ddr3_phy_core "p0"
<html>Info: "MyDDR3_master" instantiated altera_mem_if_ddr3_afi_mux "m0"

Error: Error during execution of "{C:/intelfpga/22.1std/quartus//../nios2eds/Nios II Command Shell.bat} make all 2>> stderr.txt": child process exited abnormally
Error: Execution of command "{C:/intelfpga/22.1std/quartus//../nios2eds/Nios II Command Shell.bat} make all 2>> stderr.txt" failed
Error: Nios II Command Shell.bat requires Windows Subsystem for Linux (WSL) to run.
Error: Please install WSL and try again.
Error: child process exited abnormally
Error: Cannot find sequencer/sequencer.elf

Can you help to advise how to solve this issue?

I notice it is asking me to install WSL. But my system already have WSL.

AdzimZM_Intel · ‎11-05-2023

Hello,

You can find the distro package on procedure 3 from this link: https://www.intel.com/content/www/us/en/docs/programmable/683525/21-3/installing-windows-subsystem-for-linux.html

Regards,

Adzim

在原帖中查看解决方案

AdzimZM_Intel · ‎11-03-2023

Hello,

The WSL version and Ubuntu version look okay.

What is your OS build version?

Have you installed the distro packages for NIOS?

Can you provide the snapshot of the installation progress?

Last time I did encounter similar issue because the distro packages were not installed successfully.

Regards,

Adzim

jkhoo · ‎11-05-2023

where to get distro packages for NIOS?

jkhoo · ‎11-05-2023

OS build version is windows 10 10.0.19045

AdzimZM_Intel · ‎11-05-2023

Hello,

You can find the distro package on procedure 3 from this link: https://www.intel.com/content/www/us/en/docs/programmable/683525/21-3/installing-windows-subsystem-for-linux.html

Regards,

Adzim

jkhoo · ‎11-05-2023

hi Adzim,

I install the distro package and Quartus Prime 22.1 is now working as expected.

Thank you very much, JJ

ddr3 SRAM Controller with Uniphy intel FPGA IP 22.1 failed

Design Entry|Synthesis|Compilation