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Hi. I have several modules that used the parameter in my verilog design. However it is very troublesome to do the change the value of the parameter for every module involved. Is there any way just to declare it once only on the top module? Thanks.
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Normally people use `define / `ifdef etc. to load the parameter values if this is required.
You can either set up the defines you want in a verilog file and include that at the beginning of the file list, or Quartus can set defines for you.- Mark as New
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Thanks a lot.

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