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delay in output

Altera_Forum
Honored Contributor II
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Hi all, 

 

I run P&R in quartus and get *.vho, *.sdo 

 

after running timing simulation 

 

of this ram implementation 

 

if rising_edge(clk) then 

if wr_en='1' then 

array_data(conv_integer(address))<=data_in; 

else  

address_save<=address; 

data_out<=array_data(conv_integer(address_save)); 

end if; 

 

I got delay in data_out output (not with the clk) 

 

How can I minimize this delay? I work only synchronized components. 

 

tenx 

 

ari
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Altera_Forum
Honored Contributor II
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Why are you trying to reduce the delay based on simulation results? Are you getting a negative slack in static timing analysis? If the delay is causing a problem seen in simulation but you have positive slack, then maybe you don't have the design constrained properly for timing. First constrain it properly and see whether the Fitter will make the delay better. 

 

Without testing your code in Quartus, I'm not sure whether the read portion of your "if" statement is describing two stages of registers allowing one to be at the RAM block output. I'll assume for the following that you are getting only the RAM inputs registered inside the RAM block. 

 

If the read delay is too long because of the portion of the delay within the RAM block, then that can be reduced by using the optional output registers in the RAM block. That will of course add a clock cycle of pipeline delay to the read. 

 

With a quick check I didn't find an example of RTL to describe a RAM with output registers, but there might be an example in the Quartus handbook at Volume 1, Section II, Chapter 6 "Recommended HDL Coding Styles". 

 

I suspect it would be enough to describe an ordinary register in the RTL that the RAM output feeds directly. If "Auto Packed Registers" in the "More Fitter Settings" dialog box is set to anything other than "Off", the Fitter will likely implement the RTL registers using the output registers inside the RAM block even if synthesis implements the registers outside the RAM block.
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Altera_Forum
Honored Contributor II
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Hi Brad, 

 

There are examples in precision manual (coding style - memory)  

using address_save... 

 

I understood my mistake... 

 

I forgot to analyze the tco!! and that why I got the output with delay of some ns... 

 

hope that I right... 

 

what do you think on using address_save? Is is a good way to stabilize the address signal? 

 

tenx  

 

ari
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Altera_Forum
Honored Contributor II
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--- Quote Start ---  

what do you think on using address_save? Is is a good way to stabilize the address signal? 

--- Quote End ---  

 

 

 

I don't have an opinion on the coding style. If it was recommended for Mentor Precision, then it should be fine for that tool and likely is fine for Quartus integrated synthesis too. 

 

I don't know what you mean by "stabilize the address signal". In all recent Altera device families, the RAM blocks require the address to be registered inside the RAM block at the input. Static timing analysis with proper user constraints tells you whether the address is stable at the correct time with respect to the clock.
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