derive pll clock

[Altera_Forum]

My sdc file has a derive_pll_clock to constrain the pll output clocks. 

 How do I use the pll output 0 clock to constrain an input signal.  I have tried the following which does not work  create_generated_clock -name {clk1} -divide 1 -source {pllinputclk1} [getnets {plloutput0}] set_input_delay -clock clk1 1 [get_ports {pin1}]  Fit tells me that it ignored the create_generated_clock due to empty target, which make pin1 unconstrained since clk1 does not exist.  So how do I create a clk1?

[Altera_Forum]

Hi,  

the derive_pll_clocks will create the output clocks. They have ugly names but if you need to refer to a PLL output in your constrains, that's what you should use. The PLL output clock name is something like {my_pll_instance|altpll_component|pll|clk[0]}]  Anyway, you should not constrain the input based on the PLL clock. Instead, you should create a virtual clock and constrain the input based on it.

[Altera_Forum]

set_input_delay -clock should get the name of the clock outside of the FPGA, not the name of the clock that drives the input register(Quartus already knows that). Remember that you're describing the register outside of the FPGA that is driving in. Once that is done, you have a register to register path that can be analyzed just like any other path. Go to www.alterawiki.com, click on Popular Pages and there is a TimeQuest User Guide about 10 down. The first section called Getting Started dives into these I/O in some detail.

[Altera_Forum]

If you want to get the clocks created by derive_pll_clock, in TimingQuest window, type the following command: 

write_sdc -expand

[Altera_Forum]

Or just click on Report Clocks. It's a sortable list, and I just copy the names out of the first column.