Intel® Quartus® Prime Software
Intel® Quartus® Prime Design Software, Design Entry, Synthesis, Simulation, Verification, Timing Analysis, System Design (Platform Designer, formerly Qsys)
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determining set input and set ouput delay values

alex_ander
Beginner
223 Views

Hello

I am working with understanding the timing analyzer and I have a question regarding the delay values themselves that would be used for the set_input_delay and set_output_delay. I understand somewhat how the delays are found but not entirely.

For example, the set_input_delay defines the arrival time of the input relative to a clock which would be the "clock to out" + "trace delay". I have the trace delay but i don't understand how to determine the "clock to out." Is this found in a report in the timing analyzer or how do i figure this out? same with Tsu and Th for the output delay. I basically don't understand how to find these values to plug into my set_input_delay and set_output_delay commands. 

Thanks for your help!

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4 Replies
sstrell
Honored Contributor III
206 Views

The numbers come from the spec sheet of whatever is driving into the device (tco max and min) or whatever the FPGA is driving out to (tsu and th).  I usually call them the upstream and downstream devices.

SyafieqS
Moderator
193 Views

Alex,


The value is referred to a data specification sheet for device you used. You may find all setup time, hold time to determine the input and output delay. You can refer to a part in datasheet called IO timing and there, you may find the parameter and value desired.


SyafieqS
Moderator
173 Views

Alex,


May I know if there is any update at your end?


SyafieqS
Moderator
140 Views

We do not receive any response from you to the previous reply that I have provided, thus I will put this case to close pending. Please post a response in the next 15 days to allow me to continue to support you. After 15 days, this thread will be transitioned to community support. The community users will be able to help you with your follow-up questions.


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