devkit ssram sdc constraints

[Altera_Forum]

I'm working with a Arria2 Gx devkit. 

I'm running a sopc system and ssram at 150Mhz.   I've had this system running for some time, but any recompile due to any small change might cause flaky behavior. Failed loads or random hangs.   I've not constrained the ssram to this point, I think I need to. I've read all of the guides. Several times. They cover a lot but there are a few issues with the devkit ssram kit.   - it's on a tristate bus, shared with flash. - it uses a sopc ssram unit with no code to double check - the ssram unit has a configurable latency of 2 or 3 clocks   I've read the ssram unit timing doc which covers timing calcs and skewing clocks with a pll. I've deleted the pll for now since it just makes constraining even more confusing.   I've got the following constraints in place: create_generated_clock -name pll_clk_to_ssram_dev -offset $ssram_gen_clk_offset -source $ssram_ctrlr_clk [get_ports clk_to_the_ssram]   set_output_delay -clock pll_clk_to_ssram_dev -max [expr $ssram_pcb_tpd_max + $ssram_dev_tsu]   [get_ports {tsb_addr [*] bw_n_to_the_ssram [*] bwe_n_to_the_ssram ce_n_to_the_ssram oe_n_to_the_ssram}] set_output_delay -clock pll_clk_to_ssram_dev -min [expr 0 - ($ssram_dev_th + $ssram_pcb_tpd_min)]   [get_ports {tsb_addr [*] bw_n_to_the_ssram [*] bwe_n_to_the_ssram ce_n_to_the_ssram oe_n_to_the_ssram}] set_output_delay -clock pll_clk_to_ssram_dev -max [expr $ssram_pcb_tpd_max + $ssram_dev_tsu]   [get_ports {tsb_data [*]}] set_output_delay -clock pll_clk_to_ssram_dev -min [expr 0 - ($ssram_dev_th + $ssram_pcb_tpd_min)]   [get_ports {tsb_data [*]}] set_input_delay -clock pll_clk_to_ssram_dev -max [expr $ssram_dev_tco + $ssram_pcb_tpd_max + $ssram_latency]   [get_ports {tsb_data [*]}] set_input_delay -clock pll_clk_to_ssram_dev -min [expr $ssram_dev_tckh + $ssram_pcb_tpd_min + $ssram_latency]   [get_ports {tsb_data [*]}] set_multicycle_path -from pll_clk_to_ssram_dev -to $ssram_ctrlr_clk 3  Compiling with this causes huge timing issues with the rest of the system.   Questions: - I've got a multicycle of 3 set for reads. The ssram unit expects read data 2 clocks after the address/command is sent for a total of 3 clocks. Is this the correct way to handle this ?   - On a write cycle the data needs to show up on the clock after the addr/cmd. The ssram controller document is a little fuzzy here. Assuming the data is output along with the addr/cmd, how do I constrain this ?   - I've set a false path on anything from the select_n_to_the_flash to the tsb_addr/data but I'm not sure if this the best way to handle this. How can I separate the two bus constraints ?