Intel® Quartus® Prime Software
Intel® Quartus® Prime Design Software, Design Entry, Synthesis, Simulation, Verification, Timing Analysis, System Design (Platform Designer, formerly Qsys)
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different compile results on Linux- and Windows-version of Quartus Prime


On my workstation i run windows 10 and use Quartus Prime Lite 21.1.0 and all my projects compiles fine.

After setting up CI with a linux VM on an Buildserver one of my projects refuse to compile(Same Quartus version but for linux).


I track down the problem and noticed that during Analysis & Synthese process, Quartus Prime on the Linux machine needs a lot more logic.  

During fitting it doesn't fit into the device (10CL016) and fitting fails.


I try to get the same result on the windows machine and i could reproduce the result from the linux machine.

If i set ALLOW_REGISTER_MERGING = OFF i got exactly the same result during Analysis & Synthese and Fitting fails.

So for me it looks like ALLOW_REGISTER_MERGING isn't working or is ignored on the linux machine.

Is that feature not supported ?  or is there a way to force Quartus to enable ALLOW_REGISTER_MERGING?


With Quartus Prime lite 20.0 its the same.


Regarding the link to the documentation. Is that correct that ALLOW_REGISTER_MERGING  is only supported on Arria 10 and Cyclone 10 GX? The project is with an Cyclone 10 LP,  nevertheless that feature works on the Windows version of Quartus for Cyclone 10 LP.


I run Quartus on an Ubuntu 18.04 , that shows up on the list of supported Linux distributions.

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3 Replies

You probably looking at the Pro version document, Cyclone 10 LP is supported. Check the document link below:

You can double check in the Assignment > Setting > Compiler Settings > Advanced Setting (synthesis). Search for Allow Register Merging and check that it is set as ON.

Best Regards,

Richard Tan

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I double checked it as you suggested and Quartus tells me that it is ON.

But still, I got the same Analysis & Synthesis result as i run Quartus on a Windows machine and set the feature OFF.

In the end the Design does not fit into the FPGA and Fitter fails (on the Linux VM, un Windows it still works fine).


Any other suggestions ?


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Wishing you a Happy New Year 2023!

As we do not receive any response from you on the previous question/reply/answer that we have provided. I now transition this thread to community support. Please login to ‘’, view details of the desire request, and post a feed/response within the next 15 days to allow me to continue to support you. After 15 days, this thread will be transitioned to community support. The community users will be able to help you on your follow-up questions.

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Best Regards,

Richard Tan

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