Intel® Quartus® Prime Software
Intel® Quartus® Prime Design Software, Design Entry, Synthesis, Simulation, Verification, Timing Analysis, System Design (Platform Designer, formerly Qsys)
Announcements
FPGA community forums and blogs on community.intel.com are migrating to the new Altera Community and are read-only. For urgent support needs during this transition, please visit the FPGA Design Resources page or contact an Altera Authorized Distributor.

dual port buffer

Altera_Forum
Honored Contributor II
1,303 Views

i m implementing a block where there r 2 buffer and mux,demux in which i need to store 16(4X4) each 8bit data in the buffer.so i made a 2:1 mux and a RAM but how to write the data out from mux to buffer for each clock cycle. 

i attach the block diagram of my design. can any one help me.
0 Kudos
0 Replies
Reply