- Mark as New
- Bookmark
- Subscribe
- Mute
- Subscribe to RSS Feed
- Permalink
- Report Inappropriate Content
I am trying to learn vhdl case statements and have been scratching my head trying to find the issue please help:
library ieee;
use ieee.std_logic_1164.all;library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity task1sq is
port(a,b,c,d: in std_logic;
sq: out std_logic);
end task1sq;
architecture behaviour of task1sq is
begin
process(a,b,c,d) --if implementation for prime
begin
case a & b & c & d is
when "0011" => sq <= '0';
when "0010" => sq <= '0';
when "0101" => sq <= '0';
when "0111" => sq <= '0';
when "0110" => sq <= '0';
when "1100" => sq <= '0';
when "1101" => sq <= '0';
when "1111" => sq <= '0';
when "1110" => sq <= '0';
when "1000" => sq <= '0';
when "1011" => sq <= '0';
when "1010" => sq <= '0';
when others => sq <= '1';
end case;
end process;
end behaviour;
- Mark as New
- Bookmark
- Subscribe
- Mute
- Subscribe to RSS Feed
- Permalink
- Report Inappropriate Content
The Error messages shown is:
Error (10327): VHDL error at task1sq.vhd(15): can't determine definition of operator ""&"" -- found 4 possible definitions
I have change the code below to pass the Analysis & Synthesis.
Recommend to checkout this page https://nandland.com/case-statement/ on how to use the case statement.
library ieee;
use ieee.std_logic_1164.all;library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity task1sq is
port(a,b,c,d: in std_logic;
sq: out std_logic);
end task1sq;
architecture behaviour of task1sq is
begin
process(a,b,c,d) --if implementation for prime
variable v_CONCATENATE : std_logic_vector(3 downto 0);
begin
v_CONCATENATE := a & b &c & d;
case v_CONCATENATE is
when "0011" => sq <= '0';
when "0010" => sq <= '0';
when "0101" => sq <= '0';
when "0111" => sq <= '0';
when "0110" => sq <= '0';
when "1100" => sq <= '0';
when "1101" => sq <= '0';
when "1111" => sq <= '0';
when "1110" => sq <= '0';
when "1000" => sq <= '0';
when "1011" => sq <= '0';
when "1010" => sq <= '0';
when others => sq <= '1';
end case;
end process;
end behaviour;
Best Regards,
Richard Tan
p/s: If any answer from the community or Intel Support are helpful, please feel free to give best answer or rate 4/5 survey.
Link Copied
- Mark as New
- Bookmark
- Subscribe
- Mute
- Subscribe to RSS Feed
- Permalink
- Report Inappropriate Content
FYI it helps if you post the actual error message you get instead of just a number since that gives way more info, including what line number is causing the error. I googled and found this is an undefined operator error but I still don't know what line has the issue.
My guess is that you need to have "end entity task1sq;" instead of just "end task1sq;".
- Mark as New
- Bookmark
- Subscribe
- Mute
- Subscribe to RSS Feed
- Permalink
- Report Inappropriate Content
The Error messages shown is:
Error (10327): VHDL error at task1sq.vhd(15): can't determine definition of operator ""&"" -- found 4 possible definitions
I have change the code below to pass the Analysis & Synthesis.
Recommend to checkout this page https://nandland.com/case-statement/ on how to use the case statement.
library ieee;
use ieee.std_logic_1164.all;library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity task1sq is
port(a,b,c,d: in std_logic;
sq: out std_logic);
end task1sq;
architecture behaviour of task1sq is
begin
process(a,b,c,d) --if implementation for prime
variable v_CONCATENATE : std_logic_vector(3 downto 0);
begin
v_CONCATENATE := a & b &c & d;
case v_CONCATENATE is
when "0011" => sq <= '0';
when "0010" => sq <= '0';
when "0101" => sq <= '0';
when "0111" => sq <= '0';
when "0110" => sq <= '0';
when "1100" => sq <= '0';
when "1101" => sq <= '0';
when "1111" => sq <= '0';
when "1110" => sq <= '0';
when "1000" => sq <= '0';
when "1011" => sq <= '0';
when "1010" => sq <= '0';
when others => sq <= '1';
end case;
end process;
end behaviour;
Best Regards,
Richard Tan
p/s: If any answer from the community or Intel Support are helpful, please feel free to give best answer or rate 4/5 survey.
- Mark as New
- Bookmark
- Subscribe
- Mute
- Subscribe to RSS Feed
- Permalink
- Report Inappropriate Content
Thank you for acknowledge the solution provided.
I’m glad that your question has been addressed, I now transition this thread to community support.
Thank you.
Best Regards,
Richard Tan
p/s: If any answer from the community or Intel Support are helpful, please feel free to give best answer or rate 4/5 survey.
- Subscribe to RSS Feed
- Mark Topic as New
- Mark Topic as Read
- Float this Topic for Current User
- Bookmark
- Subscribe
- Printer Friendly Page