Intel® Quartus® Prime Software
Intel® Quartus® Prime Design Software, Design Entry, Synthesis, Simulation, Verification, Timing Analysis, System Design (Platform Designer, formerly Qsys)
17261 Discussions

error regarding register inference

Altera_Forum
Honored Contributor II
‎01-13-2009 09:07 AM
1,259 Views

Hi, 

I have declared an integer type signal named q in the architecture declaration region. 

I m getting an error, which i could not comprehend... 

can't infer register for "q[18]" because its behavior does not match any supported register model  

the same error is displayed for q[0] to q[18] 

 

plz help me out... 

Thanks...
0 Kudos

Link Copied

1 Reply
Altera_Forum
Honored Contributor II
‎01-13-2009 09:17 AM
611 Views

Could you post the relevant VHDL code fragment for forum members to take a look at please? 

 

It sounds more to do with what you are doing with the q signal rather than how you have declared it
0 Kudos
Copy link
Reply

Community support is provided Monday to Friday. Other contact methods are available here.

Intel does not verify all solutions, including but not limited to any file transfers that may appear in this community. Accordingly, Intel disclaims all express and implied warranties, including without limitation, the implied warranties of merchantability, fitness for a particular purpose, and non-infringement, as well as any warranty arising from course of performance, course of dealing, or usage in trade.

For more complete information about compiler optimizations, see our Optimization Notice.