failed to load results from design analysis and cannot get the list of IPs in the design

[fey]

Hi,

I have agilex 7 i series transceiver dev kit and i'm trying to using qsfp. There are example designs  named  bts_xcvr_nrz QSFDDD and bts_xcvr_pam4 QSFPDD0_1 that use qsfp. When i compiled the designs I am getting "Logic Generation failed to load results from Design Analysis and cannot get the list of IPs in the design". Also I'm adding here the error message;  

When I compiled other example designs such as bts_xcvr_nrz SDI etc. there is not problem. It only occurs if it is QSFP.

Also when I designed basic qsfp project without any IP, I can assign QSFP pins but during compilation this error occurs;

 Any help would be appreciated.

[Kshitij_Intel]

Hi,

Can you please use an example design from the below link.

High Speed Transceiver Demo Designs - Intel Agilex® device with F-Tile - Intel Community

If this also doesn't resolve your issue. Please share your design.

Which Quartus version you are using?

Thank you,

Kshitij Goel

[Kshitij_Intel]

Hi,

As we do not receive any response from you on the previous answer that we have provided. Please login to ‘https://supporttickets.intel.com’, view details of the desire request, and post a response within the next 15 days to allow me to continue to support you. After 15 days, this thread will be transitioned to community support. The community users will be able to help you on your follow-up questions.

Thank you,

Kshitij Goel

[fey]

Hi, sorry, your response notification mail was in the spam folder. I saw your response this morning when I checked this page. I'm trying your suggestion. I'll inform you.

I'm using Quartus 22.4 with 90-day eval license and AGIB027R31B1E2VR0 device on Agilex® 7 FPGA I-Series Transceiver-SoC Development Kit (4x F-Tile).

Thanks

[fey]

Hi,

I tried these;

Intel Agilex® device I-Series PCIe development kit (ES Version):  10GbE (10G-1), Single lane Example Demo design using QSFPDD1

Intel Agilex® device I-Series PCIe development kit (ES Version): 1x8 channel 53Gbps PAM4 soft PRBS test design with KPFEC (544,514) in 2x200G Aggregate mode using FGT transceivers connected to QSFPDD1

Intel Agilex® device I-Series SI/SOC Board (ES Version) (4 F-tile device): 1x8 channel 53Gbps PAM4 soft PRBS test design with KPFEC (544,514) in 400G Aggregate mode using FGT transceivers connected to QSFPDD0

First two of  that suitable for different device type and i can not open the last one.

What must I do, which ones should I try?

Thanks.

[fey]

Hi @Kshitij_Intel ,

I'm waiting for response. I'm not sure did you not see my answer or did the thread transitioned the community. Please inform me about this.

Regards