Failed to compile project with altlvds with external pll on Cyclone V, Quartus Standard 18.1

[AntonKu]

Hi,

Could anybody give me advise what to do or try?

I compile a project with 27 lvds lines running at 384MHz sampling frequency. There is 3 input clocks for each group of 9 lines separately. The reference clocks are connected to CLK[1,2,3] pins.

If I connect LVDS lines only to pins in bank 3A, 3B, 4A and 4B all compiles fine but if i connect one pin to bank 5A (PIN_Y17 and PIN_Y18) compilation fails. PCB board is already produced and some LVDS lines are connected to bank 5A. The compilation error message is the following:

Error (14566): The Fitter cannot place 1 periphery component(s) due to conflicts with existing constraints (1 pin(s)). Fix the errors described in the submessages, and then rerun the Fitter. The Intel FPGA Knowledge Database may also contain articles with information on how to resolve this periphery placement failure. Review the errors and then visit the Knowledge Database at https://www.altera.com/support/support-resources/knowledge-base/search.html and search for this specific error message number.
Error (175020): The Fitter cannot place logic pin in region (89, 4) to (89, 9), to which it is constrained, because there are no valid locations in the region for logic of this type.
Info (14596): Information about the failing component(s):
Info (175028): The pin name(s): i_afe_d[6]
Error (16234): No legal location could be found out of 1 considered location(s). Reasons why each location could not be used are summarized below:
Info (175015): The I/O pad i_afe_d[6] is constrained to the location PIN_Y17 due to: User Location Constraints (PIN_Y17)
Info (14709): The constrained I/O pad is contained within this pin
Error (175010): Location failed detailed legality checks (1 location affected)
Info (175029): pin containing PIN_Y17

I also tried to compile the project with the newer Quartus version 21.1 but the newer version crashes after a similar compilation error message and I cannot explore the error messages. I use 18.1 version as the previous version of firmware for a similar board was compiled in 18.1 and we did some workaround for HPS and so on, so i do not want to switch to a newer version in general.

[AqidAyman_Intel]

Hello,

Can you share the full part number of Cyclone V device that you used?

Regards.

Aqid

[AntonKu]

Hi,

Thank you for reaching out.

The device is 5CSXFC6C6U23I7.

In a meanwhile I did some more testing. and figured out that I cannot rout pll signals for lvds_serdes to 5A from the same pll as for 3A, 3B, 4A and 4B.

[AqidAyman_Intel]

Hi,

May I know those three references clock is connected to which pin in your design?

[AntonKu]

Hi,

I partially solved the issue. To use lvds_serdes hardware, I had to use corner PLLs only and I cannot use the same pll output for Bank 5A and other banks at the same time. There are a few lines in documentation which describe it. 

Otherwise the clock (in the end I use the same clock input) is connected to PIN_Y15.

Regards,

Anton

[AqidAyman_Intel]

Hi Anton,

Alright, I understand. Thank you for your confirmation.

Regards,

Aqid