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I used a fast io assignment for my input and output flops
and it got ignored in the fitter (listed as such in the fitter report) I am guesing this is because of using a global clock to clock the io register? (I am using fast io register to meet timing along a path and regular flops clock to q seems high) Is there a way I can use Fast IO and clock it by a global clock (clock is output of PLL and getting distributed on a global clock line)Link Copied
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All fast I/O can be driven by a global, and in most designs, are driven. The most common reason I've seen is that there's logic between the register and the I/O cell. (Check Technology Map Viewer, not just your RTL, to see if something got synthesized differently than expected).
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hi rysc, it is a direct connecttion to the I/O (e.g. register driving output or driven by input)
I will double check. I wish the tool would say why it ignored it.
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