how to constrain my output port

[Altera_Forum]

hi Alt-Gurus: 

 I am constraining my output port say 'foo' in the usual way   set_output_delay –clock clk_A –max 3 [get_ports “foo”]  Now this port is driven by a register which is clocked by system clock 'clk' and enabled by a generated (or derived) clock 'clk_B'  The fun part (if you can call it that) is that clk_A and clk_B are derived clocks from the main system clock 'clk' generated by PLL.  Clearly my constraint above is not correct and the register will be overconstrained? Whats the way to write this?  TIA.

[Altera_Forum]

Didn't quite get the role of clk_B. 

Does it drive the output register's clock pin, or is it just used as a clock enable? If the first, then you need simply to constraint clk_B as a generated clock. If the later, you can add a multi-path exception.

[Altera_Forum]

hi, 

 CLK_B is only driving the enable of the flip flop. Are you suggesting that I do set_output_delay to CLK_A and then a set_multicycle_path between CLK_B and CLK_A? Since the external register is virtual (i.e. not part of what sta will see) will this technique work? i.e. I can't do [get_fanouts CLK_A] and expect to see the external register. In that case how do I set multicycle exception from CLK_B to this FF?

[Altera_Forum]

The clock used by set_output_delay should be whatever clock the external register is using -- I assumed it is clk_A. 

 You don't need to use get_fanouts, if it's not possible/convenient. Just use any combination of -from/-through/-to to restrict the affected paths. Ie, -from [get_ports foo] should be enough.  But multi-cycle paths can be tricky, specially when they involve different clocks. Read this first: http://pt.scribd.com/doc/14475172/multi-cycle-paths

[Altera_Forum]

Ok thanks. So what you are really saying is that I can 

Treat the external flop as a multi cycle path  And quartus sta will correctly calculate the constraint between the io flop and this external clock?

[Altera_Forum]

What I'm saying is that it's perfectly possible to apply a multicycle exception to an output path, between the output FF inside the FPGA and the virtual FF outside the FPGA.

[Altera_Forum]

thank you.