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- flop-flop simulation in ModelSim

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Altera_Forum

Honored Contributor I

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05-17-2018
05:55 AM

1,208 Views

flop-flop simulation in ModelSim

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6 Replies

Altera_Forum

Honored Contributor I

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05-17-2018
07:01 AM

72 Views

Blue means 1'bZ. We will need to code to understand the problem.

Altera_Forum

Honored Contributor I

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05-17-2018
07:17 AM

72 Views

dff code

```
module dff(clk, din, dout);
input clk;
input din;
output dout;
reg dout;
always @ (posedge clk)
begin
dout <= din;
end
endmodule
```

testbench ```
module top;
reg clk;
reg in_inf;
wire out_inf;
dff D1 (clk, in_inf, out_inf);
initial // Clock generator
begin
clk = 0;
forever# 10 clk = !clk;
end
initial //in_inf
begin
in_inf = 0;
# 28 in_inf = 1;
# 5 in_inf = 0;
end
initial //in_inf
begin
in_inf = 0;
# 48 in_inf = 1;
# 5 in_inf = 0;
end
endmodule
```

i want to see normal (not blue) signal as out_inf[1]
Altera_Forum

Honored Contributor I

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05-17-2018
10:17 AM

72 Views

Altera_Forum

Honored Contributor I

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05-17-2018
08:05 PM

72 Views

whys out_inf[0] is h'x (in the beginning), not zero?

Altera_Forum

Honored Contributor I

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05-18-2018
07:05 AM

72 Views

Altera_Forum

Honored Contributor I

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05-18-2018
01:53 PM

72 Views

can i initialize value before first clock?

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