i try to simulate [1:0]flip-flop in ModelSim and i see one normal signal(out_inf) and one blue signal(out_inf). What is it?
module dff(clk, din, dout); input clk; input din; output dout; reg dout; always @ (posedge clk) begin dout <= din; end endmoduletestbench
module top; reg clk; reg in_inf; wire out_inf; dff D1 (clk, in_inf, out_inf); initial // Clock generator begin clk = 0; forever# 10 clk = !clk; end initial //in_inf begin in_inf = 0; # 28 in_inf = 1; # 5 in_inf = 0; end initial //in_inf begin in_inf = 0; # 48 in_inf = 1; # 5 in_inf = 0; end endmodulei want to see normal (not blue) signal as out_inf
You should always look sharp at the Modelsim warnings. They tell about problem with reg dout declaration. Must be reg [1:0] dout. Or include reg in the output definition.