gate lev sim not working as expected

[Altera_Forum]

hello everybody 

im quite new in developing for FPGA. I have started wih DE0-nano board.  im learning just programming an easy FSM that performs elementary operations. i have followed the tutorial for simulating the circuit with Modelsim-Altera. no problem with the flow of functional simulation. the operations are simulated in the sequence as expected. While trying to create timing simulation with the same Modelsim (gate level simulation) my FSM does not work as expected. The state of FSM is update in not controlled way. I have made several tries and i have the suspect to have wrong code the two process statement that concurrency run. The source code is in VHDL. So same code in VHD work in functional simulation and worngly work in gate level simulation. i would like to fix this issue to learn more about FPGA.   Thank you

[Altera_Forum]

--- Quote Start ---  This picture is too small and low quality we cannot see the actual waveforms. And without the test it is impossible to tell whats going on. But the appearance of U or X usually means that something is driving them that way.  You should be able to add any signal to the wave window to trace back the drivers to see what is causing the problem.  There isnt anything obviously wrong in your code., other than not assigning next_state and finito in the "others" case to cover their state when current state is "10" or "UU" or "XX". It could be something to do with this.  Otherwise I can only assume a test bench issue.  --- Quote End ---    I have to update the issue. Decreasing the clock freq (from 100 ps to 100 ns) The machine seems working. The current state and current are properly updated. So maybe i missed to look at time analysis which is the ma freq to be use with clock   One only thing remains strange: Signal finito and next_state[] are not synthesized They don t appear on technology map netlist  And they cannot be monitored in Wave  Any idea about this last point?