gated clock

Altera_Forum · ‎01-07-2010

I have a 100 Mhz clock coming to my FPGA CLOCK100. This goes to the SOPC which has a PLL. The PLL generates a 150 MHz clock CLOCK150 which goes to my custom logic which has a PLL. The output of the PLL has CLOCK150_CUSTOM and lock. I wantuse the clock which is valid only when the PLL has locked.

I want to use locked clock

ie. CLOCK150_CUSTOM_LOCKED = CLOCK150_CUSTOM && lock;

the Design assistant says

Critical Warning: (Critical) Rule C101: Gated clock should be implemented according to the Altera standard scheme. Found 1 node(s) related to this rule.

Would you know/suggest how to get around it and suggest any better scheme of doing this.

Can I create a lock signal from the SOPC PLL?

Thanks.

Altera_Forum · ‎01-07-2010

I would typically use the lock output of the PLL to control the reset logic in my design.

Jake

Altera_Forum · ‎01-08-2010

Are you doing your design in HDl (Verilog or VHDL) or schematic?

Jake

Altera_Forum · ‎01-08-2010

The top level is a schematic.

My custom block is in verilog.

One more related question.In my SDC file I define the clock to the input port only (which is input clock to PLL in SOPC). Then I use

derive_pll_clocks to derive other clock.

Do I need to define clock to the 2nd PLL (in my custom logicic) which gets its input from the output of the 1st PLL.

I am getting some timing violations (from the output of the SOPC registers which run off the 1st PLL) to the input registers in custom logic running off 2nd PLL.