generate clock after a specific number

Altera_Forum · ‎06-19-2016

hi! I started to learn VHDL,so be patient :)

also my english is poor :cool:

but I try to explain my problem:

I try to emulate a code for generate (and delay it by a precise integer) the clock, but i can't get it.

how can I do?

so I have to generate and delay the clock, for example delay 100ps, with a fixed period from "generic (period: time: = 100ps);"

CODE:

entity test_out is

generic (period: time :=100ps;

halfperiod: time := 50ps);

port ( rit: in integer range 0 to 255; --delay for start clock

localCLK: inout std_logic

) ;

end test_out;

the architecture does not exist because i I tried different solutions but many useless and maybe stupid :D

Altera_Forum · ‎06-19-2016

Do you want to just delay a clock, or to enable its initialization after a time ?

It's in simulation, or do you want to synthesize ?

Altera_Forum · ‎06-19-2016

My project is similar to the PLL (phase locked loop), in fact I want to generate a signal to be send back to a hypothetical "phase frequency detector", then I would be initialized after a time (time that must change in relation to an "integer" value input entity) the clock signal, iterating continually until it various new "integer".

it's for simulation :D

edit: Now I'm using the operating system Ubuntu, as soon as I open windows place the architecture that I tried to make an hour ago. :D

Altera_Forum · ‎06-19-2016

--- Quote Start ---

it's for simulation

--- Quote End ---

Why not just use the 'after' clause to the signal assignment ?

Altera_Forum · ‎06-19-2016

my code is:


entity test_out is
generic (period: time :=100ps;
halfperiod: time := 50ps);
port ( rit: in integer range 0 to 255; --delay for start clock
localCLK: inout std_logic 
) ;
end test_out;
architecture beha of test_out is
signal clock: std_logic;    --used to recycle the process
signal uscita: integer range 0 to 255:=0;
begin
clock<='0','1' after halfperiod;
    process(clock)
    begin
        if (clock='1')then
        clock<= '0' after halfperiod;
        else clock <='1' after halfperiod;
        end if;
            case (rit) is
                    when 0 => uscita<=0;
                    when 1 to 10 => uscita<=1 after 1ps;
                    when 11 to 20 => uscita<=2 after 10ps;    
                    when 21 to 30 => uscita<=3 after 20ps;    
                    when 31 to 40 => uscita<=4 after 30ps;    
                    when 41 to 50 => uscita<=5 after 40ps;
                    when 51 to 60 => uscita<=6 after 50ps;    
                    when 61 to 255 => uscita<=7 after 60ps;    
            end case;
            
            case(uscita) is
                    when 0 to 255=> localCLK <='1', '0' after halfperiod;
            end case;    
    end process;
end architecture;

But with this code I can not emulate a clock signal with a duty cycle of 50% and also does not initialize after a time

I'll try again, while some idea? :D

Altera_Forum · ‎06-20-2016

You're not incrementing uscita anywhere.

Moreover, clock isn't being toogle'd.

I'm unable to understand what exactly it does.