generic map and gate level simulation

[Altera_Forum]

Hy, 

 I continue my tests of Quartus 10.0/ModelSim-Altera by the EDA Tools.  I try to simulate one example given by Altera in an exercise book for DE2 Development kit : Lab5_VHDL.pdf. In the first part of the introduction, the code for a generic counter is given.  after a minor correction (';' before the ')' of the generic part ), there is no warning and error during the compilation. The test with the RTL ModelSim is correct if the generic parameter is equal to the default value defined in the initial declaration(generic_counter.vhd). But if this value is different, the RTL simulation failed with this error :  # loading work.generic_counter(a_generic_counter)# ** fatal: (vsim-3348) port size (6) does not match actual size (4) for port '/test_generic_counter/four_bit/q'.# time: 0 ps iteration: 0 instance: /test_generic_counter/four_bit file: d:/user/noel/enseignement/cours/archi_systeme/doc_etudiants/quartus/tp1/generic_counter/generic_counter.vhd line: 31# fatal error while loading design  In addition, in the first case (same parameter value between default and instantiation) when the gate level simulation is run, it crash alone ! In the msim_transcript file the error, we find these list of problems : # loading work.generic_counter(structure)# ** error: (vsim-3733) d:/user/noel/enseignement/cours/archi_systeme/doc_etudiants/quartus/tp1/generic_counter/test_generic_counter.vhd(39): no default binding for component at 'four_bit'.# (generic 'n' is not on the entity.)# region: /test_generic_counter/four_bit# loading ieee.std_logic_arith(body)# loading stratixii.stratixii_io(structure)# ** error: (vsim-3733) generic_counter.vho(128): no default binding for component at 'clock_ai'.# (generic 'operation_mode' is not on the entity.)# region: /test_generic_counter/four_bit/clock_ai# loading stratixii.stratixii_io_register(vital_io_reg)# ** error: (vsim-3733) d:/util/langages/quartus10.0/modelsim/modelsim_ase/win32aloem/../altera/vhdl/src/stratixii/stratixii_atoms.vhd(4518): no default binding for component at 'in_reg'.# (generic 'stratixii_io_register' is not on the entity.)# region: /test_generic_counter/four_bit/clock_ai/in_reg  Can somehome explain how to use generic parameters with these new tools of simulation in Quartus 10 (RTL and Gate level)  I attached the vhdl files, project file and simulation directory in a zip file.   Thanks a lot,  EON