Combine or concatenate bus signals -Quartus II 10.0 SP1

Altera_Forum · ‎10-29-2010

Hi everyone,

I've been scouring google and these forums for the answer to my problem, but solutions to problems that resemble my own don't seem to work.

All I'm trying to do is concatenate (combine?) 4 1-bit signals into a single 4-bit signal, because I have the following module that takes a 4-bit "string" as input:

ENTITY dec_7seg IS
	PORT(hex_digit		: IN	STD_LOGIC_VECTOR(3 downto 0);
		 segment_a, segment_b, segment_c, segment_d, segment_e, 
		 segment_f, segment_g : out std_logic);
END dec_7seg;

This is what I have so far in my schematic (bdf) file (notice both bus names are "MSB[0..3]"):

You can view the file at img (dot) photobucket.com/albums/v123/TheBlackDragon7/bus_problem (dot) png

... I guess I can't post a picture as it's not my 5th post yet...

This is the closest I've gotten in terms of a successful compilation (I think) but I'm getting the following error:

Error: Width mismatch in mapping block "hex_digit" of type DEC_7SEG and instance "inst5" for signal "MSB"

I don't understand how there's a width mismatch; they're both 4 bits wide... and if it's worth mentioning, I have two modules like this, the other is "LSB[3..0]" just in case it needs to be the other direction... I've tried everything I can think of, and everything I've found in the internet about it.

Anyway I hope someone can point me in the right direction soon, thanks!

Altera_Forum · ‎10-29-2010

I don't understand the port style used in your schematic. The source side has 4 indidvidual bits, how can they connect to a single bus bar? If a symbol has individual outputs, each should have a connector and be wired to single bit signal.

If you are using a new feature of Quartus 10 schematic editor, it seems to be more confusing than helpful.

Altera_Forum · ‎10-29-2010

Aren't you supposed to get 4 single wires out of one block and then combine them into a single bus in the .bsf file that goes into another block? At least that's how Quartus 8.0 worked.

Altera_Forum · ‎10-29-2010

Yeah it works when assigning the signals that way in 10.0sp1 ... I cant really say if it's good or bad... unless I'm missing something, it's pretty similar to how this one worked:

img (dot) photobucket (dot) com/albums/v123/TheBlackDragon7/Capture.png

We just had to match up the wire names to the array of bus names.

Also, what is the bsf file? I don't have any of those file pre- or post-compilation.

Also I should note there are some major bugs in the 10.0 sp1 version (at least in the web [free] edition). One of them is assigning ports on the blocks when they're connected to anything other than a conduit (the whole program crashes). So our workaround has been converting the nodes (or buses) to a conduit, naming it if needed, mapping the I/Os from the blocks to the wires, then changing it back to a node / bus.