I have designed a normal hello world program in NIOS2 using quartus.
While running the c code its giving an error as target processor paused failed. The clk_in_reset is being connected to the debug_reset_request of the nios2_gen2_processor. am using the JTAG_UART to display it
is the problem due to any licence issue or something?
Can someone suggest me a solution to sort with this problem.
- You may face such issues when your board is in reset state and you are trying to program the .elf, Check the dip switch to which the rest pin is connected, Should be disable.
- Check the clock pin connection(pin assignments of clock and reset pins).
- Re-check if we importing correct .sopcinfo file?
- Try to recreate the eclipse project.
Let me know if this has helped resolve the issue you are facing or if you need any further assistance.
Anand Raj Shankar
(This message was posted on behalf of Intel Corporation)
Are you getting the following error when using NIOS2:
Using cable "USB-BlasterII [1-1.1]", device 1, instance 0x00
Pausing target processor: not responding.
Resetting and trying again: FAILED
Leaving target processor paused
If so, then you haven't set the reset vector of the NIOS2 processor. To fix this do the following:
- Open your NIOS2 system in QSYS/Platform Designer.
- Select the NIOS2 CPU to bring up its Properties page.
- Select the Vectors tab, and under Reset Vector MEmory : select the on-chip memory instance or the debug memory slave.
- Do the same for the Exception vector Memory.
This will depend on your design and what you want to do when a reset occurs in the design. If you want to processor to go to the start of your code after reset, set it to the on-chip memory setting.
Save and Generate the system. Build the project and try to download the code to the Kit. It should work now.
thanks for the reply
I have set the Reset vector and the Exception vector in the NIOS2 CPU properly.
The clock pin has been assigned properly. I even tried with regenerating the eclipse file but the problem still exist.
Did you regenerate the Hardware design via Quartus? After making changes to Qsys you need to regenerate and recompile the hardware design again and generate a new SOF/POF file. Along with recompiling the Eclipse software part.