getting compilation error

Altera_Forum · ‎10-16-2009

i m learning the Introduction to the Altera SOPC Builder Using VHDL Design

working on led display with switches example.

i followed every step as per instruction.i type the lights.vhd but at the time of compilation i m getting error like

Error (10500): VHDL syntax error at nios_system_inst.vhd(13) near text "nios_system_ins"; expecting "entity", or "architecture", or "use", or "library", or "package", or "configuration"

please tell me where is the problem

Altera_Forum · ‎10-16-2009

did you put any spaces in component names?

Could you open nios_system_inst.vhd and show us the lines around 13?

Altera_Forum · ‎10-16-2009

sorry that is line 2.

the error is

nios_system_inst : nios_system

port map(

out_port_from_the_LEDs => out_port_from_the_LEDs,

clk_0 => clk_0,

in_port_to_the_Switches => in_port_to_the_Switches,

reset_n => reset_n

);

--- Quote Start ---

did you put any spaces in component names?

Could you open nios_system_inst.vhd and show us the lines around 13?

--- Quote End ---

Altera_Forum · ‎10-16-2009

Oh... is it the _inst file generated by sopc builder? In that case this is just an example of how the SOPC design can be instantiated in a project. You need to copy-paste its contents to your top-level vhdl file.

Altera_Forum · ‎10-16-2009

yes _inst file isgenerated by sopc builder it is a example.

but again i m getting error please inform exactly what to do.

--- Quote Start ---

Oh... is it the _inst file generated by sopc builder? In that case this is just an example of how the SOPC design can be instantiated in a project. You need to copy-paste its contents to your top-level vhdl file.

--- Quote End ---

Altera_Forum · ‎10-16-2009

LIBRARY ieee;

USE ieee.std_logic_1164.all;

USE ieee.std_logic_arith.all;

USE ieee.std_logic_unsigned.all;

ENTITY lights IS

PORT (

SW : IN STD_LOGIC_VECTOR(7 DOWNTO 0);

KEY : IN STD_LOGIC_VECTOR(0 DOWNTO 0);

CLOCK_50 : IN STD_LOGIC;

LEDG : OUT STD_LOGIC_VECTOR(7 DOWNTO 0)

);

END lights;

ARCHITECTURE Structure OF lights IS

COMPONENT nios_system

PORT (

clk : IN STD_LOGIC;

reset_n : IN STD_LOGIC;

out_port_from_the_LEDs : OUT STD_LOGIC_VECTOR (7 DOWNTO 0);

in_port_to_the_Switches : IN STD_LOGIC_VECTOR (7 DOWNTO 0)

);

END COMPONENT;

BEGIN

-- Instantiate the Nios II system entity generated by the SOPC Builder

nios_system_inst : nios_system

port map(

out_port_from_the_LEDs => LEDG,

clk => CLOCK_50,

in_port_to_the_switches => SW,

reset_n => KEY(0)

);

END Structure;

this is the top level code but getting error

--- Quote Start ---

Oh... is it the _inst file generated by sopc builder? In that case this is just an example of how the SOPC design can be instantiated in a project. You need to copy-paste its contents to your top-level vhdl file.

--- Quote End ---

Altera_Forum · ‎10-16-2009

Is the error message still on the nios_system_inst.vhd file? If yes you should remove it from your project and put the top level VHDL instead.

Altera_Forum · ‎10-16-2009

yes there it self

Altera_Forum · ‎12-26-2011

I am also getting the same error.i removed the nios_inst.vhd file from the project. and kept the top level entity file. here problem is i dont know how to instantiate the sopc system generated file into top level entity . please help. i am also doing the same LED example. here i am uploading that file and SOPC generated files.

this is the system generated file , i am getting error here(underlined).

 --Example instantiation for system 'nios_system'
  nios_system_inst : nios_system
    port map(
      clk_0 => clk_0,
      reset_n => reset_n
    );

Altera_Forum · ‎01-16-2013

Hi,

I have the similar problem. I am doing the tutorial "Using the SDRAM on Altera’s DE2-115 Board with VHDL Designs" which have SOPC builder to generate VHDL file.

In top level entity light, there is already SOPC generated nios system is defined and instantiated as:

ARCHITECTURE Structure OF lights IS

COMPONENT nios_system

PORT ( clk_0 : IN STD_LOGIC;

reset_n : IN STD_LOGIC;

out_port_from_the_LEDs : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);

in_port_to_the_Switches : IN STD_LOGIC_VECTOR(7 DOWNTO 0);

zs_addr_from_the_sdram_0 : OUT STD_LOGIC_VECTOR(12 DOWNTO 0);

zs_ba_from_the_sdram_0 : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);

zs_cas_n_from_the_sdram_0 : OUT STD_LOGIC;

zs_cke_from_the_sdram_0 : OUT STD_LOGIC;

zs_cs_n_from_the_sdram_0 : OUT STD_LOGIC;

zs_dq_to_and_from_the_sdram_0 : INOUT STD_LOGIC_VECTOR(31 DOWNTO 0);

zs_dqm_from_the_sdram_0 : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);

zs_ras_n_from_the_sdram_0 : OUT STD_LOGIC;

zs_we_n_from_the_sdram_0 : OUT STD_LOGIC);

END COMPONENT;

BEGIN

--¡¡ Instantiate the Nios II system entity generated by the SOPC Builder.

NiosII: nios_system

PORT MAP (

clk_0 => CLOCK_50,

reset_n => KEY(0),

out_port_from_the_LEDs => LEDG,

in_port_to_the_Switches => SW,

zs_addr_from_the_sdram_0 => DRAM_ADDR,

zs_ba_from_the_sdram_0 => DRAM_BA,

zs_cas_n_from_the_sdram_0 => DRAM_CAS_N,

zs_cke_from_the_sdram_0 => DRAM_CKE,

zs_cs_n_from_the_sdram_0 => DRAM_CS_N,

zs_dq_to_and_from_the_sdram_0 => DRAM_DQ,

zs_dqm_from_the_sdram_0 => DRAM_DQM,

zs_ras_n_from_the_sdram_0 => DRAM_RAS_N,

zs_we_n_from_the_sdram_0 => DRAM_WE_N );

DRAM_CLK <= CLOCK_50;

END Structure;

Then why again separate file is generated without entity and component as:

--Example instantiation for system 'nios_system'

nios_system_inst : nios_system

port map(

out_port_from_the_LEDs => out_port_from_the_LEDs,

zs_addr_from_the_sdram_0 => zs_addr_from_the_sdram_0,

zs_ba_from_the_sdram_0 => zs_ba_from_the_sdram_0,

zs_cas_n_from_the_sdram_0 => zs_cas_n_from_the_sdram_0,

zs_cke_from_the_sdram_0 => zs_cke_from_the_sdram_0,

zs_cs_n_from_the_sdram_0 => zs_cs_n_from_the_sdram_0,

zs_dq_to_and_from_the_sdram_0 => zs_dq_to_and_from_the_sdram_0,

zs_dqm_from_the_sdram_0 => zs_dqm_from_the_sdram_0,

zs_ras_n_from_the_sdram_0 => zs_ras_n_from_the_sdram_0,

zs_we_n_from_the_sdram_0 => zs_we_n_from_the_sdram_0,

clk_0 => clk_0,

in_port_to_the_Switches => in_port_to_the_Switches,

reset_n => reset_n

);

and upon compilation giving following error:

Error (10500): VHDL syntax error at nios_system_inst.vhd(2) near text "nios_system_inst"; expecting "entity", or "architecture", or "use", or "library", or "package", or "configuration"

When I remove this additional file, the compilation is successful but I am afraid of loading on FPGA concerning it may damage with incomplete/wrong program.

Any suggestion?

Thanks in advance

Altera_Forum · ‎01-17-2013

The nios_system_inst.vhd file is just generated by SOPC builder to give you an example of how you can instantiate your project in a VHDL file. You are supposed to copy/paste the contents of that file in your top level design, but in your case it is already there. The *_inst.vhd files should never be included in your project as a file to compile directly.

Just remove it and it will be fine.

Altera_Forum · ‎02-12-2013

TO_BE_DONE

Altera_Forum · ‎02-12-2013

It is possible that the clock signal has a different name in nios_system.qip. Could you check in the generated nios_system_inst.vhd file?

Altera_Forum · ‎02-12-2013

Well, that did the trick.

Instead of clk, the generated nios_system_inst.vhd has clk_0.

Thank you very much.

Now, the next step would be using nios II.