getting quartus warnings

[Altera_Forum]

Hi,When I compile my design I keep getting warnings like this: 

 Warning (14110): No clock transition on "CMD_DECODE:u2|oTxD_DATA[6]" register due to stuck clock or clock enable Warning (14130): Reduced register "CMD_DECODE:u2|oTxD_DATA[6]" with stuck clock_enable port to stuck value GND  My design doesn't function so I believe I should solve this warnings.I checked my source code again and again and it seems fine to me.I don't understand why the clock is stuck.How can I sort those warnings out?:confused:   I'm using quartus 7.2, source code in VHDl:  entity CMD_DECODE is port(   iCLK: in std_ulogic;  iRST_n: in std_ulogic;  ----------USB JTAG----------  iRxD_DATA: in std_ulogic_vector (7 downto 0);  oTxD_DATA: out std_ulogic_vector (7 downto 0);  iRxD_Ready,iTxD_Done: in std_ulogic;  oTxD_Start: out std_ulogic;  ---------REG----------------  iREG_DATA: in std_ulogic_vector (15 downto 0);  oREG_DATA: out std_ulogic_vector (15 downto 0)   ); end entity CMD_DECODE;  architecture behav of CMD_DECODE is    shared variable CMD_Tmp: std_ulogic_vector (63 downto 0);  shared variable mREG_STEP: natural range 0 to 5;  shared variable mREG_WRn,mREG_Start,mREG_RDn: std_ulogic;  shared variable f_SRAM: std_ulogic;  ----------USB JTAG TxD Output  shared variable oREG_TxD_Start: std_ulogic;  shared variable oREG_TxD_DATA: std_ulogic_vector (7 downto 0);    signal CMD_Action: std_ulogic_vector (7 downto 0);   signal CMD_Target: std_ulogic_vector (7 downto 0);  signal CMD_ADDR: std_ulogic_vector (23 downto 0);   signal CMD_DATA: std_ulogic_vector (15 downto 0);   signal CMD_MODE: std_ulogic_vector (7 downto 0);  signal Pre_Target: std_ulogic_vector (7 downto 0);   begin   CMD_Action <= CMD_Tmp(63 downto 56);  CMD_Target <= CMD_Tmp(55 downto 48);--SRAM  CMD_ADDR <= CMD_Tmp(47 downto 24);  CMD_DATA <= CMD_Tmp(23 downto 8);  CMD_MODE <= CMD_Tmp( 7 downto 0);--NORMAL  Pre_Target <= CMD_Tmp(47 downto 40);  ----------Shift Register For Command Temp----------  process(iCLK,iRST_n,CMD_Action,iRXD_Ready,Pre_Target,CMD_MODE,CMD_Target,  CMD_DATA,iTxD_Done,iREG_DATA)  begin  if rising_edge(iCLK) then --= '1' or f_iRST_N = '1'  if iRST_n = '1'then  if CMD_Action = X"94" then  mREG_RDn := '1';  elsif CMD_Action = X"83" then  mREG_WRn := '1';  end if;    if iRXD_Ready = '1' and Pre_Target = X"A5" then  f_SRAM:='1';  if f_SRAM = '1' then  case mREG_STEP is  when 0 =>   if CMD_MODE = X"AA" and CMD_Target = X"A5" then   --check cmd mode NORMAL and target SRAM  oREG_DATA <= CMD_DATA;  mREG_Start := '1';  mREG_STEP := 1;--go to case'1'  else  mREG_STEP := 0;--cease here  f_SRAM := '0';  end if;  when 1 =>   if mREG_RDn = '1' then --if READ   mREG_STEP := 2;--go to case'2'  else  mREG_STEP := 0;--if WRITE  f_SRAM := '0';   mREG_Start := '0';--go back 0  end if;  when 2 =>   oTxD_DATA <= iREG_DATA(7 downto 0);--read FIRST BYTE from iREG_DATA   oTxD_Start <= '1';  mREG_STEP := 3;--continue processing to next case  when 3 =>   if iTxD_Done = '1' then --if tx done then stop tx  oTxD_Start <= '0';  mREG_STEP := 4;--continue processing to next case  end if;   when 4 =>  oTxD_DATA <= iREG_DATA(15 downto 8);--read NEXT BTYE from iREG_DATA  oTxD_Start <= '1';  mREG_STEP := 5;--continue processing to next case  when 5 =>   if iTxD_Done = '1' then  mREG_Start := '0';  oTxD_Start <= '0';  mREG_STEP := 0 ;--go back  f_SRAM := '0';  end if;  end case;  end if;  end if;   else   mREG_RDn :='0';  oREG_TxD_Start :='0';  mREG_WRn :='0';  mREG_Start :='0';  f_SRAM :='0';  mREG_STEP := 0 ;    end if;  else  null;  end if;   end process;   end architecture;  It is supposed to transmit data from CMP_tmp to oREG_data when CMP_action is WRITE. If CMP_action is READ it transmits data from iREG_data to oTXD_data.