global clock delay

[Altera_Forum]

hi All 

 i have 8 rgmii interfaces, 125M ddr source synchronous. each input has 1clk, 1datavalid and 4data signals. i implement it using ddio. constraint it like this:   set_input_delay -max -clock 7.300 rxd rxd rxd}] set_input_delay -min -clock 0.700 rxd rxd rxd}] set_input_delay -max -clock 7.300 rxd rxd rxd}] -add_delay -clock_fall set_input_delay -min -clock 0.700 rxd rxd rxd}] -add_delay -clock_fall set_false_path -setup -rise_from -fall_to set_false_path -setup -fall_from -rise_to set_false_path -hold -rise_from -fall_to set_false_path -hold -fall_from -rise_to   channel 0,1,4,5 timing ok,but the others turn out large hold violation. the reason is the the clock input using global clock and  when setup , the clock input to CLKCTRL is 2.738 ns  ; 11.437 ; 2.738 ; RR ; IC ; 1 ; CLKCTRL_R54 ; rxc[2]~inputCLKENA0|inclk ; when hold, the clock input to CLKCTRL is 6.817 ns ; 7.516 ; 6.817 ; RR ; IC ; 1 ; CLKCTRL_R54 ; rxc[2]~inputCLKENA0|inclk ;  so the hold timing always violation.  the clock input not a dedicated clock pin.  also i have tried regional clock and non global clock.all results are violation,due to the big clock delay difference between setup and hold. Are the delay difference true? how to improve it. ps, i cant change my pin loc.

[Altera_Forum]

the difference between setup and hold is caused by DQ pin. 

Cyclone V DQ pin used for user pin(not DDR DQ pin), always need to route through HMCPHY_RE. this routing element would cause almost 2ns differnece between setup and hold. no way to bypass it. so never use DQ pins as high speed input or output in cyclone V