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Altera_Forum
Honored Contributor I
761 Views

global clock lines

Hi, 

 

I want to define a line between two ff to be global clock line. 

because the ff in two different components I cant find 

the signals in the assignement editor (only the top module signals). 

 

Hoe can I deine this line to be global clock? 

 

tenx  

 

Ariel
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7 Replies
Altera_Forum
Honored Contributor I
63 Views

Hello Ariel: 

Is it a clock going to both the ffs or is it a data line going from a Q output of one ff to the D input of the other? I guess it will be a clock going to both the FFs. This clock will have to be coming from a pin or a PLL, in the assignment editor, in the "To" field, you can bring in your PLL output node e.g. clk0 or clk1, or you can include the pin name in this field then in the "Assignment Name" you can choose "Global Signal" and in the "Value" field you can choose "Global Clock" and that will make your clock global.  

I am not so sure about the later case when you want to make the Q output of one ff to the D input of the other ff a global clock, maybe you can find the wire connecting those two FFs from the node finder in the assignment editor and do the same as I described above for clock going into both the FFs.
Altera_Forum
Honored Contributor I
63 Views

Hello Ariel: 

Is it a clock going to both the ffs or is it a data line going from a Q output of one ff to the D input of the other? I guess it will be a clock going to both the FFs. This clock will have to be coming from a pin or a PLL, in the assignment editor, in the "To" field, you can bring in your PLL output node e.g. clk0 or clk1, or you can include the pin name in this field then in the "Assignment Name" you can choose "Global Signal" and in the "Value" field you can choose "Global Clock" and that will make your clock global.  

I am not so sure about the later case when you want to make the Q output of one ff to the D input of the other ff a global clock, maybe you can find the wire connecting those two FFs from the node finder in the assignment editor and do the same as I described above for clock going into both the FFs. 

cheers 

surfsup
Altera_Forum
Honored Contributor I
63 Views

Hi, 

Thank you very much for your answer...  

 

What I ment is that I use 50 MHz clk (DE2 board), change the frequency in the first component to 2 Hz by using counters (not PLL) and then use the new clk frequency as 

the input clk to the next component (7 segment decoder)  

I want to define this connection as global clock becuase it work but I get his message: 

 

Warning: Found 1 node(s) in clock paths which may be acting as ripple and/or gated clocks -- node(s) analyzed as buffer(s) resulting in clock skew 

Info: Detected ripple clock "frequency_change:U1|clk_2" as bufferWarning:  

 

 

tenx, 

 

ari
Altera_Forum
Honored Contributor I
63 Views

You will get that message for a ripple or gated clock regardless of whether it is global, but in most cases you should make it global as you are wanting to do. See my comments at http://www.alteraforum.com/forum/showthread.php?p=1273#post1273. You won't get the warning if you create a clock setting and assign it to the ripple clock to tell Quartus the ripple clock is on purpose, but that doesn't help with the skew concerns for synchronous paths going to or from the ripple clock domain. (The global takes care of skew for paths with both source and destination register inside the ripple clock domain.) 

 

For the "Global Signal" assignment, try the frequency_change:U1|clk_2 node name shown in the message. That's probably the same name that is listed for this clock in the Fitter compilation report at "Resource Section --> Control Signals". In general, the node name you should use in the Assignment Editor is the form of the name you see in the compilation report. 

 

Also consider using a clock enable instead of a ripple clock as I mentioned in the post I referenced above.
Altera_Forum
Honored Contributor I
63 Views

Brad thank you very much... I changed the second ff to work with en (the new clk) 

but I can't manage to define internal signal as global clk 

 

signal clk_2 : std_logic;  

begin 

process(reset,clk1)  

begin 

if reset='1' then 

counter<="0000000000000000000000001"; 

-- counter<="01"; 

clk_2<='0';  

elsif rising_edge(clk1) then 

-- if (conv_integer(counter) mod 2=0) then 

if (counter="1011111010111100001000000") then 

clk_2<=not(clk_2);  

counter<="0000000000000000000000001"; 

else  

counter<=counter+1;  

end if; 

end if; 

(the program changes 50 MHz->2 Hz) 

 

I can't detect this signal in the Assignment editor, only the signals in entity... 

 

tenx 

 

ari
Altera_Forum
Honored Contributor I
63 Views

I think you are saying you want to make a "Global Signal" assignment to clk_2. Because clk_2 is a register, most likely "clk_2" is part of a name in the node list (names of combinational signals tend to be harder to recognize in the node list). The first thing I would try is "*clk_2*" (without the quotes) in the Node Finder "Design Entry (all names)" filter. The first wildcard takes care of any hierarchy. The second wildcard takes care of any suffix that might be added to the name during compilation. Sometimes another Node Finder filter is needed to get the correct form of the name, but "Design Entry (all names)" is good enough for me most of the time. 

 

 

 

You said "work with en". The following comments are in case you are trying to use my clock enable suggestion instead of using a ripple clock. 

 

If clk_2 is being used as a clock enable rather than as an actual clock, the timing might be better with it nonglobal. If it has a high fan-out, there might be significant interconnect delay from nonglobal routing. However, a global has a significant delay for the global buffer itself. Usually the biggest advantage of global routing is to minimize skew, and skew does not matter for a clock enable as it does for a clock. Once you've figured out how to control the global routing usage, you can try the clock enable both global and nonglobal to see which has better timing. 

 

Your VHDL is creating a clock, not a clock enable, waveform for clk_2. The clock enable for a divide-by-n should be asserted every nth clock cycle of the full-speed clock (http://www.alteraforum.com/forum/showthread.php?p=2153#post2153). Instead of "clk_2<=not(clk_2);", you would assert clk_2 for one period of clk1 using "if (counter=<n_value>)" to do the divide-by-n. 

 

If clk_2 is a clock enable, then registers using the clock enable would have something like the following code that is based on a Quartus VHDL template. The registers using the clock enable most likely should be clocked by clk1, the same clock used by the clk_2 register that drives the clock enable. Even though these registers are clocked by clk1, you can use multicycles to tell Quartus they may in effect run at the clk_2 rate. The post noted just above shows how to do the multicycles in TimeQuest. If you are using the Classic Timing Analyzer with the default multicycle hold, then you can use the "Clock Enable Multicycle" assignment with the clock enable signal name in both the "from" and "to" fields. 

 

process (clk1, reset) begin if (reset = '0') then <register_variable> <= '0'; elsif (rising_edge(clk1)) then if (clk_2 = '1') then <register_variable> <= <data>; end if; end if; end process;
Altera_Forum
Honored Contributor I
63 Views

Brad, 

 

Thank you very much!!! 

 

I learnt alot from your answers... amazing! 

 

Finally i didnt use global clock because my signal hasn't high fan-out (only one ff) 

 

I will try to work with multicycles. 

 

Thank you again...  

 

I like the theory but it's not simple working with Quartus :)  

 

 

ari
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