header file in verilog / a better way to define global constants

[Altera_Forum]

Hello, I am working on a verilog project and I need to use some constants parameters in almost all of my modules. So, instead of defining them for every module, I was thinking it makes more sense to have a separate file with all the parameters and constants and include it in each module. However, I am not sure how I can do that. I tried defining them (i.e. defies.v) in a separate file and including it in my module (just like header in C/C++) with `include "defines.v". However compiler is not accepting that and I think, I am doing something wrong.  

 I would appreciate any suggestion in this regard.

[Altera_Forum]

That is the correct way. 

You may be doing something wrong..

[Altera_Forum]

Showing the syntax error message would help. 

 If you can use SystemVerilog, the putting them in a package is the way to go.

[Altera_Forum]

Thanks for the input. I am kinda swamped with some other projects now. I will definitely look into it. I might be doing something wrong.

[Altera_Forum]

Keep in mind that if your header file is just a collection of constants it is not a compile-able unit. For example, if defines.v is: 

  localparam FOO = 6; localparam BAR = "BAR";   This code needs to be scoped inside a module. So, if you are passing defines.v in a list of files to your compiler, that is your problem. Instead, you'll need to add the path to defines.v in your Verilog include path.  As an aside, I (and at least a few other people I've seen online) use .vh as the file extension for Verilog files which will be `included. This allows you to see which files define modules and which files define constants, functions, etc. Also, some tools will search a given path for files to compile based on module instantiation. This convention prevents such modes of operation from stumbling on code which can't be compiled on its own.