help!!! A simple question of a verilog fresh man

[Altera_Forum]

i have typed the following codes into" .v file" 

but after compiled , the compiler showed me:" Error: Can't synthesize current design -- Top partition does not contain any logic"   but i have make it the top level through "Project->Set top_level Entity " it still can't be solved ~~please help :p codes: module myand(a, b, c); // Input Port(s) input a,b;   // Output Port(s)   output c;   assign c=a&b;   // Additional Module Item(s) endmodule

[Altera_Forum]

please help me ,I really can't solve it

[Altera_Forum]

--- Quote Start ---  please help me ,I really can't solve it  --- Quote End ---    Hi,  check whether your toplevel is set to to "myand". have look to the attahed project.  kind regards  GPK

[Altera_Forum]

thank you ,i will try it ~:)

[Altera_Forum]

--- Quote Start ---  Hi,   check whether your toplevel is set to to "myand". have look to the attahed project.   kind regards   GPK  --- Quote End ---    thank you ,i will try it ~:)