Hello,
I generated my netlist for a submodule in my design. But when I replace the submodule (fmean.v) with the netlist fmean.vo, my output from my design is just a redline. and the internal register that is suppose to store the values, is still 0
fmean is suppose to sum the some pixel values and at the end of the cycle, output the mean.
Am I using the wrong coding style? or I am missing a step? All I did was add the .vo and save the .sdo file in the same project directory. and my timescale is 1ps/1ps same as my testbench.
I also attached waveforms
Xin and en is fine, the clock also seems fine, but everything else is red. and I am not sure why because I have an initial reset
