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help in sintax for various inputs to single internal signal vector binary and decimal

Altera_Forum
Honored Contributor I
944 Views

hello,,, i have a problem,, 

i need read 8 inputs from a digital encoder position d1,d2,d3,d4,d5,d6,d7,d8 : in std_logic, each with (0 or 1 state). but my problem is convert these inputs to a single signal : std_logic_vector(7 downto 0) in a internal signal in the (binary) in the order MSB is d8. then after this vector created to other single output (deci : out std_logic) in one data in decimal, of 0 to 255 Which is its equivalent. 

 

 

any idea that help me in a simple code sintax
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6 Replies
Altera_Forum
Honored Contributor I
96 Views

 

--- Quote Start ---  

hello,,, i have a problem,, 

i need read 8 inputs from a digital encoder position d1,d2,d3,d4,d5,d6,d7,d8 : in std_logic, each with (0 or 1 state). but my problem is convert these inputs to a single signal : std_logic_vector(7 downto 0) in a internal signal in the (binary) in the order MSB is d8. then after this vector created to other single output (deci : out std_logic) in one data in decimal, of 0 to 255 Which is its equivalent. 

 

 

any idea that help me in a simple code sintax 

--- Quote End ---  

 

 

Internal_signal <= d8 & d7 & d6 & d5 & d4 & d3 & d2 & d1;  

this concatenation, and it has no cost on resource.
Altera_Forum
Honored Contributor I
96 Views

 

--- Quote Start ---  

Internal_signal <= d8 & d7 & d6 & d5 & d4 & d3 & d2 & d1;  

this concatenation, and it has no cost on resource. 

--- Quote End ---  

 

 

Ok thank you and convert this vector of 8 bits to decimal?
Altera_Forum
Honored Contributor I
96 Views

 

--- Quote Start ---  

Ok thank you and convert this vector of 8 bits to decimal? 

--- Quote End ---  

 

 

dout <= to_integer(signed(interna_data)); 

 

it needs library numeric_std
Altera_Forum
Honored Contributor I
96 Views

 

--- Quote Start ---  

dout <= to_integer(signed(interna_data)); 

 

it needs library numeric_std 

--- Quote End ---  

 

 

ok,, in my code when compile, generate multiple output pins, not a single pin "deci" why? 

 

library ieee; 

 

use ieee.std_logic_1164.all; 

use ieee.numeric_std.all; 

 

entity joystick is 

port 

d1,d2,d3,d4,d5,d6,d7,d8 : in std_logic; 

deci : out integer range 0 to 255) ; 

 

end joystick; 

 

architecture lectura of joystick is 

 

signal val_bin : std_logic_vector(7 downto 0); 

 

begin  

 

val_bin <= d8 & d7 & d6 & d5 & d4 & d3 & d2 & d1; 

deci <= to_integer(signed(val_bin)); 

 

end lectura; 

 

i can save this output in one only value for send these after data to a serial COM for using in a program in PC? my code generate various output pins.
Altera_Forum
Honored Contributor I
96 Views

Ultimately, your integer deci will have 8 bits, and hence 8 output pins. 

If you need to send it to a PC over Serial (RS232 I assume) you will need to serialise these bits - ie. send one at a time. RS232 has a protocol you must follow - and there are many examples out there on the internet.
Altera_Forum
Honored Contributor I
96 Views

Thank you, i decide my data, leave it in one internal signal of 8 bits, now read about UART examples. 

 

library ieee; 

 

 

use ieee.std_logic_1164.all; 

use ieee.numeric_std.all; 

 

 

entity joystick is 

port 

(d1,d2,d3,d4,d5,d6,d7,d8 : in std_logic); 

--deci : out integer range 0 to 255 

end joystick; 

 

 

architecture lectura of joystick is 

 

 

signal val_bin : std_logic_vector(7 downto 0); 

signal deci : integer range 0 to 255; 

 

begin  

 

 

val_bin <= d8 & d7 & d6 & d5 & d4 & d3 & d2 & d1; 

deci <= to_integer(unsigned(val_bin)); 

 

 

end lectura;
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