Community
cancel
Showing results for 
Search instead for 
Did you mean: 
Altera_Forum
Honored Contributor I
809 Views

help with TOP I/O management

Hello, 

 

I am student who recently got my hands on DE10-nano. Up until now I was always working with Artix-7, Xilinx board. What I am trying to do is to migrate some of my projects to Intel-Quartus. What I am now fighting is an assignments of TOP IO. In Vivado(overall Xilinx products) I had constraints, where there was a IO assignments available, so-called master.xdc files. Here I will post what I am used to work with and I would like to ask someone, if could tell me how to get the same result here in Quartus. 

 

library IEEE; 

use IEEE.STD_LOGIC_1164.ALL; 

use IEEE.STD_LOGIC_UNSIGNED.ALL; 

use ieee.fixed_pkg.all; 

 

 

entity TOP is 

Port ( 

 

 

JA1 : out STD_LOGIC; -- pwm 

btnL : in STD_LOGIC; --debouncerL for state_machine - reset 

clk : in STD_LOGIC 

); 

end TOP; 

 

With this I can take oscilloscope and see the PWM if I connect it to JA1 pin. 

 

In quartus I can't find how to assign this output lets say to pin GPIO_0 D1, because I really don't know how to declare it. 

Can anyone please tell me how does this work in quartus. I have never been working with it and I think I am stuck with the Vivado way of doing thing and can't comprehend how does it work here. 

 

Thank you. 

IK
0 Kudos
1 Reply
Altera_Forum
Honored Contributor I
55 Views

Hi, 

 

I also prefer the way Vivado does the pin assignments, but Quartus is also quite simple once you understood the concept. 

 

Without highlighting the many possible ways you could go, here's what I would recommend: 

  • configure your Quartus project: select the correct FPGA, put in the VHDL files, select the top-level VHDL file 

  • in the main menu, go "Processing" -> "Start" -> "Analysis & Elaboration" 

  • once this ran successfully (i.e. no syntax errors or big logic errors), in the main menu go "Assignment" -> "Pin Planner" 

  • you'll see all I/O pins of your top level VHDL file in a table, as well as a graphical representation of the FPGA footprint; you can not drag&drop pads to signals, configure I/O standards, etc. 

  • close the Pin Planner, and run a full synthesis (main menu "Processing" > "Start Compilation") 

 

 

Hope this helps.
Reply