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Valued Contributor III
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help with TOP I/O management

Hello,<br> 

<br> 

I am student who recently got my hands on DE10-nano. Up until now I was always working with Artix-7, Xilinx board. What I am trying to do is to migrate some of my projects to Intel-Quartus. What I am now fighting is an assignments of TOP IO. In Vivado(overall Xilinx products) I had constraints, where there was a IO assignments available, so-called master.xdc files. Here I will post what I am used to work with and I would like to ask someone, if could tell me how to get the same result here in Quartus.<br> 

<br> 

library IEEE;<br> 

use IEEE.STD_LOGIC_1164.ALL;<br> 

use IEEE.STD_LOGIC_UNSIGNED.ALL;<br> 

use ieee.fixed_pkg.all;<br> 

<br> 

<br> 

entity TOP is<br> 

Port (<br> 

<br> 

<br> 

JA1 : out STD_LOGIC; -- pwm<br> 

btnL : in STD_LOGIC; --debouncerL for state_machine - reset<br> 

clk : in STD_LOGIC<br> 

);<br> 

end TOP;<br> 

<br> 

With this I can take oscilloscope and see the PWM if I connect it to JA1 pin.<br> 

<br> 

In quartus I can't find how to assign this output lets say to pin GPIO_0 D1, because I really don't know how to declare it.<br> 

Can anyone please tell me how does this work in quartus. I have never been working with it and I think I am stuck with the Vivado way of doing thing and can't comprehend how does it work here.<br> 

<br> 

Thank you.<br> 

IK
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Valued Contributor III
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After synthesizing your design, use the Pin Planner from the Tools menu to assign top-level signals to pins. You can drag and drop onto the picture of the device package or double-click location cells in the All Pins list at the bottom to select a location.

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Valued Contributor III
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This seems as really nasty, so if I wanted to assign 50 pins I would be manually be grabbing them one by one in pin assignment? Whats even more dreadful to me is, that one has to look in schematics to even get what and where that pin really is. 

 

Can it be declared in top directly? Is there really no way how do declare them? 

 

Maybe I have asked bad question. I have found something called DE10_nano_goldentop. It is funny thing where a possible I/O pins are. Unfortunately this is only for Verilog.  

//////////// GPIO_0, GPIO connect to GPIO Default ////////// 

inout [35:0] GPIO_0, 

 

Is there a way how to get VHDL reference for my board? 

 

How does one in quartus comfirm from VHDL which pin was assigned and where? Let's say we have project where 10 people are working on. If the basement is declared and assigned to PIN only in PIN assigner, then if there one come to a file after some else he/she doesn't know what these pins were used for. For example: 

 

library IEEE; 

use ieee.std_logic_1164.all; 

use ieee.std_logic_unsigned.all; 

 

entity TOP is 

Port ( 

x1 : out std_logic; --pwm 

reset : in std_logic; -- resets on high 

clk : in std_logic 

); 

 

Tell me please, as this is a TOP, where does x1 really go ? :) One can assemble it to 10 different pins and each person would do it differently. But if there was a way to assign it like: 

 

library IEEE; 

use ieee.std_logic_1164.all; 

use ieee.std_logic_unsigned.all; 

 

entity TOP is 

Port ( 

GPIO_0_D1 : out std_logic; --pwm 

reset : in std_logic; -- resets on high 

clk : in std_logic 

); 

 

then there would be no way someone would assign it somewhere else. Or am I missing something? 

 

sstrell thank you for answer, but could you elaborate it please? What would you do, if possible step_by_step, if you wanted to assign this top to GPIO_0_D1. This would really helped me a lot.
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Valued Contributor III
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You can shift-click to select multiple pins and choose options for how to place them: one by one or in rows or columns. You can also add synthesis attributes to your code for I/O locations, but I don't usually see people doing that because it leaves no room for moving them later in the design process, if necessary. If your board is already fixed, then synthesis attributes may be the way to go. 

 

You cannot turn top-level signal names into pin assignments the way you have mentioned. The only way to do it directly in your code would be with synthesis attributes. 

 

The whole point of the Pin Planner is to make it easy to find valid I/O locations for your design. Not every pin can be used as a GPIO and some pins have special functionality. With the Pin Planner, you can make sure you are using valid pins for your design by perform checks (I/O Assignment Analysis) to make sure that your pin assignments are valid for your selected target device.
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Valued Contributor III
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in Pin-Planner you can also enter the Location directly in the list at the bottom rather drag and drop to the I/O Pin. Additionally the Pin I/O are stored in the *.qsf File in the Project Directory (but you need to be careful editing these files normally generated by Quartus).

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