Verilog language does not support such datatypes for synthesis. Use need to use a 16, 24, 32, 64 bit wire / register as a port that you pass the encoded floating value thru.
If you are just writing verilog (like for a testbench) you can use the real datatype which will pass floating point numbers thru ports. No synthesis, however.
You cannot use float in Verilog, you may define x number of bits for the supported data types. There are 2 data types in Verilog - net and variable data types.
The nets represent the physical connection between structural entities and do not store any value on its own. The variables are used in procedural blocks which can hold value. You may refer to Data Types support list in https://www.intel.com/content/www/us/en/programmable/quartushelp/current/index.htm#hdl/vlog/vlog_list_sys_vlog_d1627e211.htm