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Beginner
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how do you map an array to a std_logic_vector?

For eg: I have an array -

type REG_TYPE is array (0 to FIR_ORDER-1) of signed (DATA_WIDTH+COEFF_WIDTH-1 downto 0)

 

and another signal X: REG_TYPE.

 

As per the need of the requirement, i would be calling some adders and multipliers to meet the objective.

And adders have the type of STD_LOGIC_VECTOR.

 

Upon Portmapping, i have come to a situation where my result(STD_LOGIC_VECTOR) is getting values from REG_TYPE.

 

This is showing an error. Please provide me guidance

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2 Replies
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New Contributor I
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>> This is showing an error.

 

What error?

 

It would be a lot easier to help you if you would show your code.

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Highlighted
6 Views

Can you provide the code and full error message?

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