how many nanosecond used for after for ethernet to send 32 bits one by one

[Altera_Forum]

i harded code with counter to send a ethernet frame, any alternatives to do smartly? if using after x ns, how many nano seconds i use for this and how? 

 process(clk) VARIABLE last_clk : std_logic := U; VARIABLE counter : integer := 0; VARIABLE last_counter : integer := 0; begin while (whilelooptrue = enableit) loop if SW(0) = '1' then beginwrite <= '1'; ff_tx_wren_enable <= enableit; startpacket <= enableit; tx_data <= preamble; startpacket <= disableit; if (clk = '0') AND (last_clk = '1') then if (counter = 0) then tx_data <= preamble; end if; if (counter = 1) then tx_data <= preamble; end if; if (counter = 2) then tx_data <= preamble; end if; if (counter = 3) then tx_data <= preamble; end if; if (counter = 4) then tx_data <= preamble; end if; if (counter = 5) then tx_data <= preamble; end if; if (counter = 6) then tx_data <= preamble; end if; if (counter = 7) then tx_data <= SFD; end if; if (counter = 8) then tx_data <= dest_mac_addr1; end if; if (counter = 9) then tx_data <= dest_mac_addr2; end if; if (counter = 10) then tx_data <= dest_mac_addr3; end if; if (counter = 11) then tx_data <= dest_mac_addr4; end if; if (counter = 12) then tx_data <= dest_mac_addr5; end if; if (counter = 13) then tx_data <= dest_mac_addr6; end if; if (counter = 14) then tx_data <= src_mac_addr1; end if; if (counter = 15) then tx_data <= src_mac_addr2; end if; if (counter = 16) then tx_data <= src_mac_addr3; end if; if (counter = 17) then tx_data <= src_mac_addr4; end if; if (counter = 18) then tx_data <= src_mac_addr5; end if; if (counter = 19) then tx_data <= src_mac_addr6; end if; if (counter = 20) then tx_data <= wholepacketlength1; end if; if (counter = 21) then tx_data <= wholepacketlength2; end if; if (counter = 22) then tx_data <= payload; end if; if (counter = 23) then tx_data <= CheckSumResult4; end if; if (counter = 24) then tx_data <= CheckSumResult3; end if; if (counter = 25) then tx_data <= CheckSumResult2; end if; if (counter = 26) then endpacket <= enableit; tx_data <= CheckSumResult1; end if; last_counter := counter; counter := counter + 1; end if; if (clk = '1') AND (last_clk = '0') then if (counter >= 26) then endpacket <= disableit; ff_tx_wren_enable <= disableit; end if; end if; else beginwrite <= '0'; end if; end loop; last_clk := clk; end process;

[Altera_Forum]

I am assuming here that you are talking directly to the PHY and aren't using a MAC. Although in that case I don't understand why you have a "startpacket" signal as it isn't a signal used with the PHY. 

To answer your question you just send one word per clock cycle, so as long as clk is the same clock than the one used to communicate with the PHY, your method should be good. I have two other comments about your code: startpacket <= enableit; tx_data <= preamble; startpacket <= disableit;This is exactly equivalent to tx_data <= preamble; startpacket <= disableit;The first line is useless as you overwrite the startpacket signal with disableit without delay. if SW(0) = '1' then ... if (clk = '0') AND (last_clk = '1') thenI don't think this with synthesize properly, and it won't simulate properly because it will set tx_data back to preamble at each rising edge of the clock. And in any case it isn't the recommended way. The recommended way to design a clocked process is as follows: if falling_edge(clk) then -- or if (clk = '0') and clk'event then ... if SW(0) = '1' then ...And you don't need to do separate things on the rising and falling edges of the clock. First Quartus doesn't know how to synthesize this, and second with a synchronous interface you can do everything on the same edge of the clock, including updating your counter value.