how to correctly assign to these variables

[Altera_Forum]

1. 

Error (10500): VHDL syntax error at tether2.vhd(152) near text "IN"; expecting an identifier ("in" is a reserved keyword), or a string literal    constant ff_tx_mod : IN STD_LOGIC_VECTOR (1 DOWNTO 0) := '00';    2. Error (10500): VHDL syntax error at tether2.vhd(142) near text "'"; expecting "(", or an identifier, or unary operator    variable gm_tx_d2 :STD_LOGIC_VECTOR (7 DOWNTO 0) := '00';   3. Error (10500): VHDL syntax error at tether2.vhd(152) near text "IN"; expecting an identifier ("in" is a reserved keyword), or a string literal    constant ff_tx_mod : IN STD_LOGIC_VECTOR (1 DOWNTO 0) := '00';    4. Warning (10639): VHDL warning at Transmit2.vhd(115): constant value overflow    constant preamble : STD_LOGIC_VECTOR (7 DOWNTO 0) := '5555555555555555';

[Altera_Forum]

Hi, 

 These are very basic things. I recommend you find a good VHDL book and learn the syntax.   constant ff_tx_mod : IN STD_LOGIC_VECTOR (1 DOWNTO 0) := '00';  should be:  constant ff_tx_mod : STD_LOGIC_VECTOR (1 DOWNTO 0) := "00";  You use IN to define an input to an entity.   variable gm_tx_d2 :STD_LOGIC_VECTOR (7 DOWNTO 0) := '00'; should be:  variable gm_tx_d2 :STD_LOGIC_VECTOR (7 DOWNTO 0) := "00000000";  because your vector has eight elements.   constant ff_tx_mod : IN STD_LOGIC_VECTOR (1 DOWNTO 0) := '00';   get rid of the IN since this is not an input to the entity.   constant preamble : STD_LOGIC_VECTOR (7 DOWNTO 0) := '5555555555555555';  You define an eight bit vector and then try to stuff a huge number into it. The biggest unsigned number that can be represented by eight bits is 255.  Mark.

[Altera_Forum]

really thank you very much, your reply very helpful 

 preamble in mac address using 55555555 , is it a hex number or integer in double colon?

[Altera_Forum]

Hi, 

 The Ethernet preamble is 14 instances of 0x5 (binary 0101), for which you'll need 7 bytes. This can be written many different ways in VHDL, but to write it as hex use:  x"55555555555555"  which is interpreted as an unsigned vector. You could also write it as:  16#55555555555555#  which is interpreted as an integer literal.  Mark.

[Altera_Forum]

is STD_LOGIC_VECTOR (7 DOWNTO 0) assumed assign is integer ? 

 if in hex number, can it be written in  constant preamble : STD_LOGIC_VECTOR (7 DOWNTO 0) := x'55555555555555';

[Altera_Forum]

Hi, 

 > constant preamble : STD_LOGIC_VECTOR (7 DOWNTO 0) := x'55555555555555';  That would still be wrong as you're trying to assign a 56 bit number to an eight bit vector. Do this:  constant preamble : STD_LOGIC_VECTOR (55 DOWNTO 0) := x'55555555555555';  Good luck.  Mark.

[Altera_Forum]

You need to use double quotes, " for a string.  

constant preamble : STD_LOGIC_VECTOR (55 DOWNTO 0) := x"55555555555555";  Also, this is just a hex string, not a decimal integer. a std_logic_vector is not an integer, it is a collection of bits. To assign it from an integer, you need to convert it via the numeric_std package  constant preamble : STD_LOGIC_VECTOR (55 DOWNTO 0) := std_logic_vector( to_unsigned( 555555, 56 ) );

[Altera_Forum]

i got it, success compile

[Altera_Forum]

--- Quote Start ---  You need to use double quotes, " for a string.   --- Quote End ---    Ah, my bad. I just copied his line and didn't notice he'd used single quotes.    --- Quote Start ---  Also, this is just a hex string, not a decimal integer. a std_logic_vector is not an integer, it is a collection of bits. To assign it from an integer, you need to convert it via the numeric_std package  constant preamble : STD_LOGIC_VECTOR (55 DOWNTO 0) := std_logic_vector( to_unsigned( 555555, 56 ) );  --- Quote End ---    True for older VHDL, but VHDL-1993 onwards will correctly convert the hex string to a std_logic_vector without needing to convert it explicitly. Not that yours is wrong, just two ways to skin this cat :). Personally I prefer the cleaner look of the direct assignment without lots of explicit type conversions.  Mark.

[Altera_Forum]

--- Quote Start ---   True for older VHDL, but VHDL-1993 onwards will correctly convert the hex string to a std_logic_vector without needing to convert it explicitly. Not that yours is wrong, just two ways to skin this cat :). Personally I prefer the cleaner look of the direct assignment without lots of explicit type conversions.  --- Quote End ---    the x"12345" is just that, a hex string, its not an integer or anything, its just a string of bits. The OP started talking about integers, which is not a hex string, and thus requires the type conversion.

[Altera_Forum]

Aren't integers limited to 32-bit values in VHDL? I think the standard just says "at least" 32 bits but I don't know what Quartus actually uses. 

Anyway I'm not sure it is safe to use something like 16#55555555555555#. I think it's better to stick to vectors (including the signed and unsigned types) when dealing with values that need more than 32 bits.