how to accelerate the compilation speed

[Altera_Forum]

I am currently working on a big project(at least for me ),there are some big parts of the project are verified and works fine ,but every time i did some modification to the part that i work on ,the whole project has to compile again including the verified parts . i used to think use the parallel compilation and smart compilation will solve the compile time ,but it turns out that they didn't do much help  

is there anyway that i can fix the "Verified" parts unchanged in the compilation and reduce the total compilation time?

[Altera_Forum]

You can use Design Partitions,along with smart compilation enabled which will significantly reduce your compilation time  

 The synthesized Partions which are unchanged will not be synthesized again   But this will increase the overall chip area occupied slightly

[Altera_Forum]

Thanks , is there any material about this "Design Partition" you mentioned ? I am using Quartus II 9.0, what function does it this " Design Partition " corresponds to in Quartus II 9.0?

[Altera_Forum]

Please find this  

 www.altera.com/literature/hb/qts/qts_qii51015.pdf

[Altera_Forum]

I have a further question on design partitioning. Scenario : I have a working NIOS subsystem created in Qsys that I am not going to use for a while. I instantiate the NIOS subsystem at my top-level, fully-synthesized the design and then created a design partition for the NIOS subsystem ONLY (along with a logic-lock region). I set the Netlist type to "Post-Fit". Fully synthesized the design again.  

 But, when I make simple (adding a two-input XOR) changes to my top-level, the synthesis procedure still compiles the entire NIOS subsystem. The Partition Merge report shows "Source File" for "Netlist Type Used" because it says "detected changes in source file". I have however not even touched the NIOS subsystem.   So I need help on understanding why the synthesis tool keeps recompiling the NIOS subsystem in spite of my design partition (and no manual changes to the subsystem on my part).  Let me know if you need further details on my design, thanks.  Bharath  PS : For now, I have removed all design partitions and commented out the subsystem to speed up synthesis, place-and-route etc. but I would really like to understand what is going on.

[Altera_Forum]

I believe the synthesis report has an Incremental Compilation section that shows which files it thinks have changed. Be sure to look at this. (And make sure you're re-using the /incremental_db directory)

[Altera_Forum]

Hi Bharath 

 http://www.altera.com/literature/hb/...s_qii51015.pdf (http://www.altera.com/literature/hb/qts/qts_qii51015.pdf)  You can see in the page No 25 for a clear description that whenever Quartus detects changes in the Top level file It re-compiles the sub modules also  There is an option of setting the Rapid recompile to on, and make the net-list type of the partition that is changed to source manually  Also there is another option described "Forcing Use of the Compilation Netlist When a Partition has Changed" by setting On the Advanced tab,  "turn on the ignore changes in source files"   But it was cautioned to be used by advanced users only

[Altera_Forum]

Thanks all, I will repost if we still have issues with incremental compilation. For now, we are simulating a different part of the design and it will probably be a while before we synthesize again. 

 Bharath