how to apply timing constrain for this code

[Altera_Forum]

hi forum,  

 i just want to know how to properply apply constrains in timequest for this , and i want to false path and cirtical path or multicycle path in the following design. thanks a lot  regards,  baba   library ieee; use ieee.std_logic_1164.all; use ieee.std_logic_arith.all; use ieee.std_logic_unsigned.all;  ENTITY xxyy IS PORT( clock : IN STD_LOGIC;  ho_total : IN std_logic_vector(11 downto 0);  h_forpch : IN std_logic_vector(7 downto 0);  h_swd : IN std_logic_vector(8 downto 0);  ve_total : IN std_logic_vector(11 downto 0);  v_forpch : IN std_logic_vector(3 downto 0);  v_swd : IN std_logic_vector(3 downto 0);  ho_on : IN std_logic_vector(9 downto 0);  ve_on : IN std_logic_vector(5 downto 0);  DE_out : OUT STD_LOGIC;  hs_out : OUT STD_LOGIC;  vs_out : OUT STD_LOGIC); END xxyy ;  ARCHITECTURE rtl OF xxyy IS  SIGNAL hs, vs,v_on_h,v_on_v : STD_LOGIC := '1'; SIGNAL h_count,v_count : STD_LOGIC_VECTOR( 11 DOWNTO 0 ) := (others=>'0');  begin   PROCESS(clock,ho_total,h_forpch,h_swd) BEGIN  if rising_edge(clock)   IF ( h_count = ho_total) THEN -- horizontal counter  h_count <= (others=>'0');   ELSE   h_count <= h_count + '1';   END IF;    IF (h_count <= h_swd and h_count >= h_forpch) THEN -- h sync generation  hs <= '1';  ELSE hs <= '0';  END IF;    IF (h_count >= ho_on) THEN -- video on horizontal for active displaygeneration  v_on_h <= '1';  ELSE   v_on_h <= '0';  END IF;     IF (v_count >= ve_on) THEN -- video on vertical for active displaygeneration  v_on_v <= '1';  ELSE v_on_v <= '0';  END IF;   end if;    end process;  PROCESS(hs,ve_total,v_forpch,v_swd,h_count,v_count) BEGIN  if rising_edge(hs) -- vertical counter  v_count <= v_count + '1';   end if;  IF (v_count = ve_total) THEN -- vertical counter clear  v_count <= (others=>'0');  end if;   IF (v_count <= v_swd and v_count >= v_forpch) THEN -- v sync generation  vs <= '1';   ELSE   vs <= '0';  END IF;  end process;     hs_out <= hs;  vs_out <= vs;  DE_out <= v_on_h AND v_on_v;    end rtl;

[Altera_Forum]

I take it you know how to make clock constraints and I/O constraints, and are just looking for multicycles and false paths? To be honest, that's a function of the design, and nobody knows this design as well as you do. If you want to be more specific and describe how a specific path behaves and if it's a multicycle or false path, that might make more sense. 

(Just quickly, false paths are generally between asynchronous clocks, so there's no way to determine what the requirement should be since the clocks are constantly changing their relationship. These are easy to constrain with a false_path, but difficult to design for since all sorts of other things need to be taken into account(metastability, different delays to differnet destinations, etc.) Multicycles generally means the data transfers through the registers at a lower rate. For example, if the source and destination clocks are both 10ns, but the data only goes through on every other clock cycle, than you can multicycle those paths. That's just a really quick description, as there are plenty of other cases.

[Altera_Forum]

You need to clean up your VHDL before you work on the timing constraints. Besides a couple of syntax errors for missing "then"s, you have some problems with your process statements. The sensitivity lists for registered logic should contain only the clock and asynchronous control signals like reset. The second process statement should be changed to separate process statements for registered logic and for combinational logic. See http://www.alteraforum.com/forum/showthread.php?t=1025 for coding style references in the Quartus handbook and elsewhere. 

 After you have changed to a standard coding style, consider changing the hs ripple clock to a clock enable. See http://www.alteraforum.com/forum/showthread.php?t=2388 for more information about this. If the hs clock changed to a clock enable is doing a divide-by-n function, then you can use a multicycle setup of n and multicycle hold of n-1. I can't tell whether hs can be reduced to a simple divide by n that can use a clock enable.