how to connect PLL output to default pin

[Altera_Forum]

I am using Quartus II 9.0 to synthesize for a Cyclone III part. I want the C0 output of PLL4 to go to pin T16. According to the pin planner, this is the default output for PLL4. 

 I can assign the c0 in a port map to an output signal at my highest level entity, and then connect that signal in the pin planner to pin T16. It works, but I get a warning that the default assignment for that pin has been overridden.  Anything else I try doesn't seem to work.  Does anyone know how to inform the fitter that you want it to use the default assignment for this pin and have it connected to PLL4?  [I have submitted this question to Altera support, but never had an answer. :mad: ]   thanks Micheal

[Altera_Forum]

can you provide the full part number that you are using?

[Altera_Forum]

Yes: 

 EP3C55F484C8

[Altera_Forum]

I wanted to add to my original post: 

 this is a general problem. When you instantiate a component using the megawizard, how can you get Quartus to associate a given instance of a PLL with a physical resource on the target device?  There must be a mechanism, otherwise what is the use of having a default assignment of PLL4_c0 to pin T16, to take the example in my design?  I have poked around in the assignment editor, but even though there is a category labeled PLL, it is empty in my case. I must have missed an (undocumented) opportunity to tell Quartus that I am using PLLs on this device...  Please see attached vhdl file ...

[Altera_Forum]

i created a new project, created a PLL, assigned the c0 output to T16, assigned the input clock to AA12 (a local dedicated clock input), and i do not see any warnings.

[Altera_Forum]

What was the mechanism you used to do this? 

 Did you map the C0 output to a signal which is defined as an output of your top-level entity, then assign that signal to pin T16? If so that is what I did, and I get the warning.  Or did you do something a bit different?  thanks Micheal

[Altera_Forum]

no i used the PLL as the top level of the design. i can try putting it in the top level entity later.